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W53300 Datasheet(PDF) 3 Page - Winbond |
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W53300 Datasheet(HTML) 3 Page - Winbond |
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3 / 9 page  W53300/W53320 Publication Release Date: March 1999 - 3 - Revision A2 BLOCK DIAGRAM LCD DRIVER PC STACK (8 Levels) (896*4) Timer 0 (8 Bit) Timing Generator SEG0 to SEG47 V2 ~ V6 XIN XOUT Timer 1 (8 Bit) Watch Dog Timer (18/14 Bit) VDD2 ALU ACC Divider (14/10 Bit) X32I X32O ROM (16K*20) DH1, DH2 COM0 to COM31 RAM Interrup & Hold Mode Release Special Register . . HCF HEF IEF EVF FLAG1 PSR0 MR1 MLDH PEF SPCH FLAG0 LUP2 PM0 . . LUP3 LUP0 LUP1 LUC RP0L RP0M RP0H PORT RB PORT RD PORT RC PORT RE Speech Dual Tone Melody (1K*22 ROM) (384Kbit ROM) PORT RA VLCD PUMP CIRCUIT MLD_play MLD_busy SPC_busy SPC_busy TONE TEST RA0~3 RB0~3 RD0~3 RC0~ 3 RE0 to 3 VDD LED1 LED2 VSS1 RES VDDP PWM1 PWM2 ROSC VDD3 VSS2 |
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