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PE3293 Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers

Part No. PE3293
Description  1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis
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PE3293 Datasheet(HTML) 6 Page - List of Unclassifed Manufacturers

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PE3293
Product Specification
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0015~02C
| UTSi  CMOS RFIC SOLUTIONS
Page 6 of 18
Table 6. DC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IDD
3 V supply current
C10, C20 = 00 (both PLLs on)
4.0
mA
Istby
Total standby current
5.0
50
µA
Digital inputs: Clock, Data, LE
VIH
High level input voltage
VDD = 2.7 to 3.3 volts
0.7 x VDD
V
VIL
Low level input voltage
VDD = 2.7 to 3.3 volts
0.3 x VDD
V
IIH
High level input current
VIH = VDD = 3.3 volts
-1
+1
µA
IIL
Low level input current
VIL = 0, VDD = 3.3 volts
-1
+1
µA
Reference Divider input: fr
IIHR
Input current
VIH = VDD = 3.3 volts
+25
µA
IILR
Input current
VIL = 0, VDD = 3.3 volts
-25
µA
Digital output: foLD
VOLD
Output voltage LOW
Iout = 1 mA
0.4
V
VOHD
Output voltage HIGH
Iout = -1 mA
VDD – 0.4
V
Charge Pump outputs: CP1, CP2
ICP - Source
-70
µA
ICP - Sink
Drive current
VCP = VDD / 2
-70
µA
ICPL
Leakage current
0.5 V < VCP < VDD – 0.5 volt
-5
5
nA
ICP – Source
vs.
ICP - Sink
Sink vs. source mismatch
VCP = VDD / 2, TA = 25° C
10
%
ICP vs TA
Output current vs. temperature
VCP = VDD / 2
10
%
ICP vs. VCP
Output current magnitude
variation vs. voltage
0.5 V < VCP < VDD – 0.5 volt, TA = 25° C
10
%


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