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PE3293 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part No. PE3293
Description  1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis
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PE3293 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

 
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PE3293
Product Specification
PEREGRINE SEMICONDUCTOR CORP.  | http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 3 of 18
Figure 3. Pin Configuration: 24-Pin BCC (Top View)
Table 2. Pin Descriptions
Pin No.
Pin Name
Type
Description
1
N / C
No connect.
2
CP1
Output
Internal charge-pump output from PLL1 for connection to a loop filter for driving the input of an external
VCO.
3
GND
Ground
4
fin1
Input
Prescaler input from the PLL1 (RF) VCO. Maximum frequency is 1.8 GHz.
5
Dec1
Power supply decoupling pin for PLL1. A capacitor should be placed as close as possible to this pin and be
connected directly to the ground plane.
6
VDD1
PLL1 prescaler power supply (FlexiPower 1).
7
N / C
No connect.
8
fr
Input
Reference frequency input.
9
GND
Ground.
10
foLD
Output
Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and
data out of the shift register. CMOS output (see Table 11, foLD Programming Truth Table).
11
Clock
Input
CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift
register.
12
Data
Input
Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits.
13
N / C
No connect.
14
LE
Input
Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded into
one of the four appropriate latches (as assigned by the control bits).
15
VDD2
PLL2 prescaler power supply. 3.3 kohm resistor to VDD.
16
Dec2
Power supply decoupling pin for PLL2. A capacitor should be placed as close as possible to this pin and be
connected directly to the ground plane.
17
fin2
Input
Prescaler input from the PLL2 (IF) VCO. Maximum frequency is 550MHz.
18
GND
Ground.
19
N / C
No connect.
20
CP2
Output
Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external
VCO.
21
VDD
(Note 1)
Power supply voltage input. Input may range from 2.7 V to 3.3 V. A bypass capacitor should be placed as
close as possible to this pin and be connected directly to the ground plane.
N/C
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
21
22
23
24
CP2
V
DD
V
DD
N/C
V
DD
N/C
N/C
Data
Clock
f
oLD
GND
f
r
N/C
GND
f
in2 Dec2
V
DD2 LE
CP1
GND
f
in1 DEC1
V
DD1


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