© VITESSE SEMICONDUCTOR CORPORATION

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4/10/00

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VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC6511

Deserializer/Reclocker at 1.485Gb/s

SMPTE-292M Serializer, Deserializer, and

G52311-0, Rev. 2.0

Serial Input

The differential PECL-style input, SDI/SDI, is the input source for 1.485 Gb/s SMPTE-292M data in the

Deserializer and Reclocker modes. This input is ignored in Serializer mode.

Clock Recovery Unit

The serial data on the SDI/SDI input is sent to the digital Clock Recovery Unit (CRU) which extracts the

clock and retimes the data. This digital CRU is completely monolithic and requires no external components.

Furthermore, it automatically locks onto data when present and locks to REFCLK when data is not present. This

eliminates the need for the system to control the CRU. The CRU is enabled only in the Deserializer and Deseri-

alizer/Reclocker modes.

Deserializer

The reclocked serial bit stream is deserialized into a 20-bit parallel character. D0 is serially received prior to

D1. The VSC6511 provides a TTL recovered clock, RCLK at one twentieth of the serial baud rate. This clock is

generated by dividing down the high-speed clock from the CRU which is phase locked to the serial data.

The

deserializer is enabled only in the Deserializer and Deserializer/Reclocker modes.

If serial input data is not present, or does not meet the required baud rate, the VSC6511 will continue to

produce a recovered clock so that downstream logic may continue to function. The RCLK output frequency

under these circumstances will differ from their expected frequency by less than +1%.

Descrambler and NRZI Decoder

The VSC7152 contains a descrambler/NRZI Decoder which processes the recovered serial data and out-

puts unscrambled and NRZI decoded serial data from the deserializer. The serial scrambled data is descrambled/

NRZI decoded assuming data has been scrambled/NRZI encoded with the following combined generator poly-

LOW. The descrambler is enabled only in the Deserializer mode.

CRC Checker

The 20-bit data from the Descrambler is sent to the CRC Checker where a running CRC checksum is con-

tinuously calculated. As 20-bit data is sent out of the chip, the CRC output pin is asserted if the checksum did

not meet the value expected. This error is asserted from the first CRC Error until the end of the line. A controller

monitors the 20-bit data out of the serializer for SAV/EAV frames in order to control the CRC Checker. The

CRC Checker is enabled only in Deserializer and Deserializer/Reclocker modes.

Frame Aligner

The VSC6511 monitors the serial data stream for SAV/EAV characters. These characters should be located

within each line of video data. If SAV/EAV is not detected within the period of one line, the Framer sends a sig-

nal to the Deserializer to shift the data one bit. The Framer then looks for SAV/EAV and the process repeats

until properly detected. Without these patterns, serial data is not aligned in any way with the parallel outputs.

The Framer outputs a once-per-line (LINE), Horizontal ANCilliary period (HANC), 1.001/1.000 output (1.001)

and a once-per-frame (FRAME) signal indicating the detection of the proper synchronization pulse in the data.

Framing is enabled only in Deserializer mode.

The Frame Aligner also outputs the LINE, FRAME and HANC outputs signals. The timing of these signals

is indicated below.