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AD5934YRSZ-REEL7 Datasheet(PDF) 6 Page - Analog Devices |
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AD5934YRSZ-REEL7 Datasheet(HTML) 6 Page - Analog Devices |
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6 / 31 page  AD5934 Data Sheet Rev. E | Page 6 of 31 I2C SERIAL INTERFACE TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted (see Figure 2). Table 2. Parameter1 Limit at TMIN, TMAX Unit Description fSCL 400 kHz max SCL clock frequency t1 2.5 µs min SCL cycle time t2 0.6 µs min tHIGH, SCL high time t3 1.3 µs min tLOW, SCL low time t4 0.6 µs min tHD, STA, start/repeated start condition hold time t5 100 ns min tSU, DAT, data setup time t62 0.9 µs max tHD, DAT, data hold time 0 µs min tHD, DAT, data hold time t7 0.6 µs min tSU, STA, setup time for repeated start t8 0.6 µs min tSU, STO, stop condition setup time t9 1.3 µs min tBUF, bus free time between a stop and a start condition t10 300 ns max tR, rise time of SDA when transmitting 0 ns min tR, rise time of SCL and SDA when receiving (CMOS compatible) t11 300 ns max tF, fall time of SCL and SDA when transmitting 0 ns min tF, fall time of SDA when receiving (CMOS compatible) 250 ns max tF, fall time of SDA when receiving 20 + 0.1 Cb3 ns min tF, fall time of SCL and SDA when transmitting Cb 400 pF max Capacitive load for each bus line 1 Guaranteed by design and characterization, not production tested. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH MIN of the SCL signal) to bridge the undefined falling edge of SCL. 3 Cb is the total capacitance of one bus line in pF. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD. SCL SDA START CONDITION REPEATED START CONDITION STOP CONDITION t9 t3 t10 t11 t4 t4 t6 t2 t5 t7 t8 t1 Figure 2. I2C Interface Timing Diagram |
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