AD5934_17 datasheet(23/31 Pages) AD | Impedance Converter, Network Analyzer

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Data Sheet

AD5934

Rev. E | Page 23 of 31

Valid Real/Imaginary Data

This bit is set when data processing for the current frequency

point is finished, indicating real/imaginary data available for

reading. The bit is reset when a start frequency sweep/increment

frequency/repeat frequency DDS command is issued. In addition,

this bit is reset to 0 when a reset command is issued to the

control register.

Frequency Sweep Complete

This bit is set when data processing for the last frequency point in

the sweep is complete. This bit is reset when a start frequency

sweep command is issued to the control register. This bit is also

reset when a reset command is issued to the control register.

REAL AND IMAGINARY DATA REGISTERS (16 BITS—

ADDRESS 0x95, REGISTER ADDRESS 0x96,

These registers contain a digital representation of the real and

imaginary components of the impedance measured for the

current frequency point. The values are stored in 16-bit, twos

complement format. To convert this number to an actual

impedance value, the magnitude,

)

Imaginary

(Real

2 +

, must

be multiplied by an admittance/code number (called a gain

factor) to give the admittance and the result inverted to give the

impedance. The gain factor varies for each ac excitation

voltage/gain combination.

The default value upon reset: these registers are not reset at

power-up or on receipt of a reset command. Note that the data

in these registers is only valid if Bit D1 in the status register is

set, indicating that the processing at the current frequency point

is complete.

AD5934 Datasheet(PDF) 23 Page - Analog Devices