Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

AD5932 Datasheet(PDF) 21 Page - Analog Devices

Part No. AD5932
Description  Programmable Frequency Scan Waveform Generator
Download  28 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD5932 Datasheet(HTML) 21 Page - Analog Devices

Back Button AD5932 Datasheet HTML 17Page - Analog Devices AD5932 Datasheet HTML 18Page - Analog Devices AD5932 Datasheet HTML 19Page - Analog Devices AD5932 Datasheet HTML 20Page - Analog Devices AD5932 Datasheet HTML 21Page - Analog Devices AD5932 Datasheet HTML 22Page - Analog Devices AD5932 Datasheet HTML 23Page - Analog Devices AD5932 Datasheet HTML 24Page - Analog Devices AD5932 Datasheet HTML 25Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 28 page
background image
Data Sheet
AD5932
Rev. C | Page 21 of 28
AD5932 TO 80C51/80L51 INTERFACE
Figure 36 shows the serial interface between the AD5932 and
the 80C51/80L51 microcontroller. The microcontroller is operated
in Mode 0 so that TxD of the 80C51/80L51 drives SCLK of the
AD5932, while RxD drives the serial data line SDATA. The FSYNC
signal is again derived from a bit programmable pin on the port
(P3.3 being used in the diagram). When data is to be transmitted to
the AD5932, P3.3 is taken low. The 80C51/80L51 transmits data in
8-bit bytes; thus, only eight falling SCLK edges occur in each cycle.
To load the remaining eight bits to the AD5932, P3.3 is held low
after the first eight bits have been transmitted, and a second write
operation is initiated to transmit the second byte of data. P3.3 is
taken high following completion of the second write operation.
SCLK should idle high between the two write operations. The
80C51/80L51 outputs the serial data in an LSB-first format. The
AD5932 accepts the MSB first (the four MSBs being the control
information, the next four bits being the address, while the eight
LSBs contain the data when writing to a destination register).
Therefore, the transmit routine of the 80C51/80L51 must
consider this and rearrange the bits so that the MSB is output first.
AD59321
80C51/80L511
1ADDITIONAL PINS OMITTED FOR CLARITY.
P3.3
RxD
TxD
FSYNC
SDATA
SCLK
Figure 36. 80C51/80L51 to AD5932 Interface
AD5932 TO DSP56002 INTERFACE
Figure 37 shows the interface between the AD5932 and the
DSP56002. The DSP56002 is configured for normal mode,
asynchronous operation with a gated internal clock (SYN = 0,
GCK = 1, SCKD = 1). The frame sync pin is generated internally
(SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0),
and the frame sync signal frames the 16 bits (FSL = 0). The
frame sync signal is available on Pin SC2, but it must be inverted
before being applied to the AD5932. The interface to the
DSP56000/DSP56001 is similar to that of the DSP56002.
AD59321
DSP560021
1ADDITIONAL PINS OMITTED FOR CLARITY.
SC2
STD
SCK
FSYNC
SDATA
SCLK
Figure 37. DSP56002 to AD5932 Interface


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn