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AD5932 Datasheet(PDF) 17 Page  Analog Devices 

AD5932 Datasheet(HTML) 17 Page  Analog Devices 
17 / 28 page Data Sheet AD5932 Rev. C  Page 17 of 28 SETTING UP THE FREQUENCY SCAN As stated in the Frequency Profile section, the AD5932 requires certain registers to be programmed to enable a frequency scan. The Setting Up the Frequency Scan section discusses these registers in more detail. Start Frequency (FSTART) To start a frequency scan, the user needs to tell the AD5932 what frequency to start scanning from. This frequency is stored in a 24bit register called FSTART. If the user wishes to alter the entire contents of the FSTART register, two consecutive writes must be performed: one to the LSBs and the other to the MSBs. Note that for an entire write to this register, Control Bit B24 (D11) should be set to 1, with the LSBs programmed first. In some applications, the user does not need to alter all 24 bits of the FSTART register. By setting Control Bit B24 (D11) to 0, the 24bit register operates as two 12bit registers, one containing the 12 MSBs and the other containing the 12 LSBs. This means that the 12 MSBs of the FSTART word can be altered independently of the 12 LSBs and vice versa. The addresses of both the LSBs and the MSBs of this register are shown in the following bit map. D15 D14 D13 D12 D11 to D0 1 1 0 0 12 LSBs of FSTART <11…0> 1 1 0 1 12 MSBs of FSTART <23…12> Frequency Increments (∆f) The value in the Δf register sets the increment frequency for the scan and is added incrementally to the current output frequency. Note that the increment frequency can be positive or negative, thereby giving an increasing or decreasing frequency scan. At the start of a scan, the frequency contained in the FSTART register is output. Next, the frequency (FSTART + Δf ) is output. This is followed by (FSTART + Δf + Δf), and so on. Multiplying the Δf value by the number of increments (NINCR) and adding it to the start frequency (FSTART) give the final frequency in the scan. Mathematically, this final frequency/stop frequency is represented by FSTART + (NINCR × Δf) The Δf register is a 23bit register that requires two 16bit writes to be programmed. Table 7 gives the addresses associated with both the MSB and LSB registers of the Δf word. Table 7. Δf Register Bits D15 D14 D13 D12 D11 D10 to D0 Scan Direction 0 0 1 0 12 LSBs of ∆f <11…0> N/A 0 0 1 1 0 11 MSBs of Δf <22…12> Positive Δf (FSTART + Δf) 0 0 1 1 1 11 MSBs of Δf <22…12> Negative ∆f (FSTART − Δf) Number of Increments (NINCR) An end frequency is not required on the AD5932. Instead, this end frequency is calculated by multiplying the frequency increment value (Δf) by the number of frequency steps (NINCR) and adding it to/subtracting it from the start frequency (FSTART); that is, FSTART + NINCR × Δf. The NINCR register is a 12bit register, with the address shown in the following bit map. D15 D14 D13 D12 D11 D0 0 0 0 1 12 bits of NINCR <11…0> The number of increments is programmed in binary fashion, with 000000000010 representing the minimum number of frequency increments (two increments) and 111111111111 representing the maximum number of increments (4095). Table 8. NINCR Data Bits D11 … D0 Number of Increments 0000 0000 0010 Two frequency increments. This is the minimum number of frequency increments. 0000 0000 0011 Three frequency increments. 0000 0000 0100 Four frequency increments. … … … … 1111 1111 1110 4094 frequency increments. 1111 1111 1111 4095 frequency increments. Increment Interval (tINT) The increment interval dictates the duration of the DAC output signal for each individual frequency of the frequency scan. The AD5932 offers the user two choices: • The duration is a multiple of cycles of the output frequency. • The duration is a multiple of MCLK periods. The desired choice is selected by Bit D13 in the tINT register as shown in the following bit map. D15 D14 D13 D12 D11 D10 to D0 0 1 0 x x 11 bits <10…0> Fixed number of output waveform cycles. 0 1 1 x x 11 bits <10…0> Fixed number of clock periods. Programming of this register is in binary form, with the minimum number being decimal 2. Note that 11 bits, D10 to D0, of the register are available to program the time interval. As an example, if MCLK = 50 MHz, then each clock period/base interval is (1/50 MHz) = 20 ns. If each frequency must be output for 100 ns, then <00000000101> or decimal 5 must be pro grammed to this register. Note that the AD5930 can output each frequency for a maximum duration of 211 − 1 (or 2047) times the increment interval. 
