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AD5932 Datasheet(PDF) 15 Page - Analog Devices
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AD5932 Datasheet(HTML) 15 Page - Analog Devices
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Rev. C | Page 15 of 28
THEORY OF OPERATION
The AD5932 is a general-purpose, synthesized waveform
generator capable of providing digitally programmable
waveform sequences in both the frequency and time domain.
The device contains embedded digital processing to provide a
scan of a user-programmable frequency profile allowing enhanced
frequency control. Because the device is preprogrammable, it
eliminates continuous write cycles from a DSP/microcontroller
in generating a particular waveform.
The frequency profile is defined by the start frequency (F
the frequency increment (Δf) and the number of increments
per scan (N
). The increment interval between frequency
, is either user-programmable with the interval
automatically determined by the device (auto-increment mode),
or externally controlled via a hardware pin (external increment
mode). For automatic update, the interval profile can be for
either a fixed number of clock periods or a fixed number of
output waveform cycles.
In the auto-increment mode, a single pulse at the CTRL pin starts
and executes the frequency scan. In the external-increment mode,
the CTRL pin also starts the scan, but the frequency increment
interval is determined by the time interval between sequential
0/1 transitions on the CTRL pin.
An example of a 2-step frequency scan is shown in Figure 30.
Note the frequency swept output signal is continuously available
and is, therefore, phase continuous at all frequency increments.
NUMBER OF STEP CHANGES
Figure 30. Operation of the AD5932
When the AD5932 completes the frequency scan from
frequency start to frequency end, that is, from F
incrementally to (F
× Δf), it continues to output
the last frequency in the scan (see Figure 31). Note that the
frequency scan time is given by (N
+ 1) × t
Figure 31. Frequency Scan
The AD5932 has a standard 3-wire serial interface that is
compatible with SPI®, QSPI™, MICROWIRE™, and DSP
Data is loaded into the device as a 16-bit word under the
control of a serial clock input, SCLK. The timing diagram for
this operation is shown in Figure 4.
The FSYNC input is a level-triggered input that acts as a frame
synchronization and chip enable. Data can be transferred into the
device only when FSYNC is low. To start the serial data transfer,
FSYNC should be taken low, observing the minimum FSYNC to
SCLK falling edge setup time, t
. After FSYNC goes low, serial
data is shifted into the device's input shift register on the falling
edges of SCLK for 16 clock pulses. FSYNC may be taken high
after the 16th falling edge of SCLK, observing the minimum
SCLK falling edge to FSYNC rising edge time, t
FSYNC can be kept low for a multiple of 16 SCLK pulses and
then brought high at the end of the data transfer. In this way, a
continuous stream of 16-bit words can be loaded while FSYNC is
held low. FSYNC should only go high after the 16th SCLK falling
edge of the last word is loaded.
The SCLK can be continuous, or, alternatively, the SCLK can
idle high or low between write operations.
POWERING UP THE AD5932
When the AD5932 is powered up, the part is in an undefined
state and, therefore, must be reset before use. The seven registers
(control and frequency) contain invalid data and need to be set
to a known value by the user. The control register should be the
first register to be programmed, as this sets up the part. Note
that a write to the control register automatically resets the internal
state machines and provides an analog output of midscale, because
it performs the same function as the INTERRUPT pin. Typically,
this is followed by a serial loading of all the required scan
parameters. The DAC output remains at midscale until a
frequency scan is started using the CTRL pin.
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