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AD5932 Datasheet(PDF) 6 Page - Analog Devices

Part No. AD5932
Description  Programmable Frequency Scan Waveform Generator
Download  28 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD5932 Datasheet(HTML) 6 Page - Analog Devices

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AD5932
Data Sheet
Rev. C | Page 6 of 28
TIMING SPECIFICATIONS
All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and are timed from a voltage level of (VIL + VIH)/2 (see Figure 3 to
Figure 6). DVDD = 2.3 V to 5.5 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
Limit at TMIN, TMAX
Unit
Conditions/Comments
t1
20
ns min
MCLK period
t2
8
ns min
MCLK high duration
t3
8
ns min
MCLK low duration
t4
25
ns min
SCLK period
t5
10
ns min
SCLK high time
t6
10
ns min
SCLK low time
t7
5
ns min
FSYNC to SCLK falling edge setup time
t8
10
ns min
FSYNC to SCLK hold time
t9
5
ns min
Data setup time
t10
3
ns min
Data hold time
t11
2 × t1
ns min
Minimum CTRL pulse width
t12
0
ns min
CTRL rising edge to MCLK falling edge setup time
t13
10 × t1
ns typ
CTRL rising edge to VOUT delay (initial pulse, includes initialization)
8 × t1
ns typ
CTRL rising edge to VOUT delay (initial pulse, includes initialization)
t14
1 × t1
ns typ
Frequency change to SYNC output, each frequency increment
t15
2 × t1
ns typ
Frequency change to SYNC output, end of scan
t16
20
ns max
MCLK falling edge to MSBOUT
1
Guaranteed by design, not production tested.
MASTER CLOCK AND TIMING DIAGRAMS
MCLK
t3
t2
t1
Figure 3. Master Clock
SCLK
FSYNC
SDATA
D15
D14
D2
D1
D0
D15
D14
t7
t9
t6
t8
t10
t5
t4
Figure 4. Serial Timing
MCLK
CTRL
VOUT
t12
t11
t13
Figure 5. CTRL Timing


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