AK7735 datasheet(37/142 Pages) AKM

Part #	AK7735

Description	Dual DSP with 4chADC 4chDAC 4chSRC

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Manufacturer	AKM [Asahi Kasei Microsystems]

Direct Link	http://www.akm.com

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37 / 142 page

[AK7735]

016014707-E-00

2016/12

- 37 -

■ I2C Interface

(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;

AVSS=DVSS1=DVSS2=DVSS3=0V)

1. I

2C: Fast Mode

Parameter

Symbol

Min.

Typ.

Max.

Unit

I

2C Timing

SCL clock frequency

fSCL

-

400

kHz

Bus Free Time Between Transmissions

tBUF

1.3

-

s

Start Condition Hold Time (prior to first Clock pulse)

tHD:STA

0.6

-

s

Clock Low Time

tLOW

1.3

-

s

Clock High Time

tHIGH

0.6

-

s

Setup Time for Repeated Start Condition

tSU:STA

0.6

-

s

SDA Hold Time from SCL Falling

tHD:DAT

0

-

s

SDA Setup Time from SCL Rising

tSU:DAT

0.1

-

s

Rise Time of Both SDA and SCL Lines

tR

-

0.3

s

Fall Time of Both SDA and SCL Lines

tF

-

0.3

s

Setup Time for Stop Condition

tSU:STO

0.6

-

s

Pulse Width of Spike Noise Suppressed By Input Filter

tSP

0

-

50

ns

Capacitive load on bus

Cb

-

400

pF

2. I

2C: Fast Mode Plus

Parameter

Symbol

Min.

Typ.

Max.

Unit

I

2C Timing

SCL clock frequency

fSCL

-

1

MHz

Bus Free Time Between Transmissions

tBUF

0.5

-

s

Start Condition Hold Time (prior to first Clock pulse)

tHD:STA

0.26

-

s

Clock Low Time

tLOW

0.5

-

s

Clock High Time

tHIGH

0.26

-

s

Setup Time for Repeated Start Condition

tSU:STA

0.26

-

s

SDA Hold Time from SCL Falling

tHD:DAT

0

-

s

SDA Setup Time from SCL Rising

tSU:DAT

0.05

-

s

Rise Time of Both SDA and SCL Lines

tR

-

0.12

s

Fall Time of Both SDA and SCL Lines

tF

-

0.12

s

Setup Time for Stop Condition

tSU:STO

0.26

-

s

Pulse Width of Spike Noise Suppressed By Input Filter

tSP

0

-

50

ns

Capacitive load on bus

Cb

-

550

pF

tHIGH

SCL

SDA

VIH3

tLOW

tBUF

tHD:STA

tR

tF

tHD:DAT

tSU:DAT

tSU:STA

Stop

Start

Stop

tSU:STO

VIL3

VIH3

VIL3

tSP

Figure 12. I

2C Interface Timing

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