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AK7707 Datasheet(PDF) 25 Page - Asahi Kasei Microsystems

Part # AK7707
Description  Multi Core DSP with SRC
Download  34 Pages
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Manufacturer  AKM [Asahi Kasei Microsystems]
Direct Link  http://www.akm.com
Logo AKM - Asahi Kasei Microsystems

AK7707 Datasheet(HTML) 25 Page - Asahi Kasei Microsystems

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[AK7707]
016011589-E-00-PB
2016/11
- 25 -
SPI Interface
1. Clock Reset
(CKRESETN bit = “0”)
(Ta =
−40~85ºC; VDD12 = 1.14~1.3V; AVDD = 3.13~3.47V; VDD33 = 3.13~3.47V; TVDD1 = 1.7~3.47V;
TVDD2 = 1.7~3.47V; VSS1~6 = 0V; CL = 20pF)
Parameter
Symbol
Min.
Typ.
Max.
Unit
μP Interface Signal
SCLK Frequency
fSCLK
3.5
MHz
SCLK Low-level Width
tSCLKL
135
ns
SCLK High-level Width
tSCLKH
135
ns
Microcontroller
→ AK7707
CSN High-level Width
tWRQH
300
ns
From
CSN “↑” to PDN “↑”
tRST
360
ns
From
PDN “↑” to CSN “↓”
tIRRQ
1
ms
From
CSN “↓” to SCLK “↓”
tWSC
300
ns
From
SCLK “↑” to CSN “↑”
tSCW
480
ns
SI Latch Setup Time
tSIS
120
ns
SI Latch Hold Time
tSIH
120
ns
AK7707
→ Microcontroller
Delay Time from SCLK
“↓” to SO Output
tSOS
120
ns
SO Output Hold Time from SCLK “↑” (* 29)
tSOH
120
ns
Note:
* 29. Except when writing the 8th bit of the command code.
2. PLL Lock
(CKRESETN bit = “1” and PLL is locked)
(Ta =
−40~85ºC; VDD12 = 1.14~1.3V; AVDD = 3.13~3.47V; VDD33 = 3.13~3.47V; TVDD1 = 1.7~3.47V;
TVDD2 = 1.7~3.47V; VSS1~6 = 0V; CL = 20pF)
Parameter
Symbol
Min.
Typ.
Max.
Unit
μP Interface Signal
SCLK Frequency
(* 30)
fSCLK
7
MHz
SCLK Low-level Width
tSCLKL
60
ns
SCLK High-level Width
tSCLKH
60
ns
Microcontroller
→ AK7707
CSN High-level Width
tWRQH
150
ns
From
CSN “↑” to PDN “↑”
tRST
180
ns
From
PDN “↑” to CSN “↓”
tIRRQ
1
ms
From
CSN “↓” to SCLK “↓”
tWSC
150
ns
From
SCLK “↑” to CSN “↑”
tSCW
240
ns
SI Latch Setup Time
tSIS
60
ns
SI Latch Setup Time
tSIH
60
ns
AK7707
→ Microcontroller
Delay Time from SCLK
“↓” to SO Output
tSOS
60
ns
SO Output Hold Time from SCLK “↑”
(* 29)
tSOH
60
ns
Note:
* 30. It takes maximum 10ms to lock PLL after setting
CKRESETN bit = “0”→ “1”.
Control registers can always be accessed by 7MHz.


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