AK7707 datasheet(22/34 Pages) AKM

Part #	AK7707

Description	Multi Core DSP with SRC

Download	34 Pages

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Manufacturer	AKM [Asahi Kasei Microsystems]

Direct Link	http://www.akm.com

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22 / 34 page

[AK7707]

016011589-E-00-PB

2016/11

- 22 -

■ Serial Data Interface (SDIN1~SDIN8, SDOUT1~SDOUT8)

(Ta =

−40~85ºC; VDD12 = 1.14~1.3V; AVDD = 3.13~3.47V; VDD33 = 3.13~3.47V; TVDD1 = 1.7~3.47V;

TVDD2 = 1.7~3.47V; VSS1~6 = 0V; CL=20pF)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Slave Mode

Delay Time from BICK “↑” to LRCK

(* 26)

tBLRD

10

ns

Delay Time from LRCK to

BICK “↑”

(* 26)

tLRBD

10

ns

Serial Data Input Latch Setup Time

tBSIDS

10

ns

Serial Data Input Latch Hold Time

tBSIDH

5

ns

Delay Time from LRCK to Serial Data Output

(* 27)

tBSOD1

22

ns

Delay Time from BICK

“↓” to Serial Data Output

(* 26, * 28)

tBSOD2

5

30

ns

Master Mode

BICK Frequency

fBCLK

32, 48, 64,128,

256,512

fs

BICK Duty Cycle

50

%

Delay Time from BICK “↓” to LRCK

(* 28)

tMBL

-10

10

ns

Serial Data Input Latch Setup Time

tBSIDS

20

ns

Serial Data Input Latch Hold Time

tBSIDH

10

ns

Delay Time from BICK

“↓” to Serial Data Output

(* 27, * 28)

tBSOD

10

ns

Notes:

* 26. Measured from BICK

“↓” when the BICK polarity is inverted by setting BCKPx bit = “1”.

* 27. Measured from BICK

“↑” when the BICK polarity is inverted by setting BCKPx bit = “1”.

* 28. Set SDOPHx bit to

“1” and the data should be output based on BICK “↑” if BICK is faster than

12.288MHz

such as when using TDM256 mode with 96kHz sampling frequency in slave mode.

SDOPHx bit must be set to

“0” in master mode.

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AK7707 Datasheet(PDF) 22 Page - Asahi Kasei Microsystems

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