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NCD2400M Datasheet(PDF) 17 Page - IXYS Corporation

Part No. NCD2400M
Description  Wide Capacitance Range, Non-volatile Digital Programmable Capacitor
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Maker  IXYS [IXYS Corporation]
Homepage  http://www.ixys.com
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NCD2400M Datasheet(HTML) 17 Page - IXYS Corporation

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INTEGRATED CIRCUITS DIVISION
NCD2400M
R01
www.ixysic.com
17
3.6.4 Read Operation
With a valid device address and the R/W bit set to 1, the device will execute a Read Operation. Following the device
address byte from the Master, the NCD2400M slave will output 4 bytes on the SDA bus: BYTE 3 will be output first;
followed by BYTE 2; then BYTE 1; and last BYTE 0.
BYTE 3: bits <7:4> = 0x8; bit <3> is nv/v, the current Operating Mode (1 = Non-Volatile), (0 = Volatile);
bits<2:1> Address of last written Non-Volatile nibble; and bit <0> is vr<8>, the Volatile Register MSB
BYTE 2: bits <7:0> are vr<7:0>, the Volatile Register bits <7:0>
BYTE 1: bits <7:4> = 0x0; bit <3> is “a”, the I
2C Chip ID address LSB; bits <2:1> = 0x2; and
bit <0> is nv<8>, the Non-Volatile memory MSB
BYTE 0: bits <7:0> are nv<7:0>, the Non-Volatile memory bits <7:0>.
A read command instructs the NCD2400M to perform two tasks. Data in Non-Volatile Memory is passed to the CDAC
non-volatile controller register which configures the programmable capacitor when operating in the Non-Volatile
Mode. And second, the NCD2400M will output its stored contents onto the SDA bus as described above. The content
output onto the bus of the Volatile Register and the Non-Volatile Memory is the last data written into these locations.
Reading the device after a power up reset and before a write to the Volatile Register will return a value of 0x000 for
the contents of the Volatile Register. This is because the Volatile Register is cleared at power up.
When the device is returned to the Non-Volatile Mode by means of the “Set Non-Volatile Mode” command, a read
operation will return the last value written into the Volatile Register. Data format of a read operation is illustrated in the
diagram below
READ OPERATION.
Master to slave
Chip ID + R
Slave to Master
BYTE 3
BYTE 2
BYTE 1
BYTE 0
NV_Addr <1:0>
0
10
0
VR <8>
NV/V
11
0
0
00
01
VR <7:0>
0000
0
1
a
NV <8>
NV <7:0>
a
7-Bit Address
R / W
S Chip ID + R A
BYTE 3
A
BYTE 2
A
BYTE 1
A
BYTE 0
A P


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