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5L35021 Datasheet(PDF) 29 Page - Integrated Device Technology

Part # 5L35021
Description  VersaClock 3S Programmable Clock Generator
Download  37 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

5L35021 Datasheet(HTML) 29 Page - Integrated Device Technology

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©2017 Integrated Device Technology, Inc.
November 29, 2017
5L35021 Datasheet
Byte 21: PLL2 Spread Spectrum Control
Byte 22: PLL2 Spread Spectrum Control
Byte 23: PLL2 Period Control
Byte 15h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL2_STEP_DELTA[7]
PLL2 spread step size control delta bit 7
R/W
0
Bit 6
PLL2_STEP_DELTA[6]
PLL2 spread step size control delta bit 6
R/W
0
Bit 5
PLL2_STEP_DELTA[5]
PLL2 spread step size control delta bit 5
R/W
0
Bit 4
PLL2_STEP_DELTA[4]
PLL2 spread step size control delta bit 4
R/W
0
Bit 3
PLL2_STEP_DELTA[3]
PLL2 spread step size control delta bit 3
R/W
0
Bit 2
PLL2_STEP_DELTA[2]
PLL2 spread step size control delta bit 2
R/W
0
Bit 1
PLL2_STEP_DELTA[1]
PLL2 spread step size control delta bit 1
R/W
0
Bit 0
PLL2_STEP_DELTA[0]
PLL2 spared step size control delta bit 0
R/W
0
Byte 16h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL2_STEP[15]
PLL2 spread step size control bit 15
R/W
0
Bit 6
PLL2_STEP[14]
PLL2 spread step size control bit 14
R/W
0
Bit 5
PLL2_STEP[13]
PLL2 spread step size control bit 13
R/W
0
Bit 4
PLL2_STEP[12]
PLL2 spread step size control bit 12
R/W
0
Bit 3
PLL2_STEP[11]
PLL2 spread step size control bit 11
R/W
0
Bit 2
PLL2_STEP[10]
PLL2 spread step size control bit 10
R/W
0
Bit 1
PLL2_STEP[9]
PLL2 spread step size control bit 9
R/W
0
Bit 0
PLL2_STEP[8]
PLL2 spread step size control bit 8
R/W
0
Byte 17h
Name
Control Function
Type
0
1
PWD
Bit 7
PLL2_PERIOD[7]
PLL2 period control bit 7
R/W
0
Bit 6
PLL2_PERIOD[6]
PLL2 period control bit 6
R/W
0
Bit 5
PLL2_PERIOD[5]
PLL2 period control bit 5
R/W
0
Bit 4
PLL2_PERIOD[4]
PLL2 period control bit 4
R/W
0
Bit 3
PLL2_PERIOD[3]
PLL2 period control bit 3
R/W
0
Bit 2
PLL2_PERIOD[2]
PLL2 period control bit 2
R/W
0
Bit 1
PLL2_PERIOD[1]
PLL2 period control bit 1
R/W
0
Bit 0
PLL2_PERIOD[0]
PLL2 period control bit 0
R/W
0


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