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SC16C650AIN40 Datasheet(PDF) 9 Page - NXP Semiconductors |
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SC16C650AIN40 Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 50 page Philips Semiconductors SC16C650A UART with 32-byte FIFO and IrDA encoder/decoder Product data Rev. 04 — 20 June 2003 9 of 50 9397 750 11622 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. [1] In sleep mode, XTAL2 is left floating. 6. Functional description The SC16C650A provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The SC16C650A is fabricated with an advanced CMOS process to achieve low drain power and high speed requirements. The SC16C650A is an upward solution that provides 32 bytes of transmit and receive FIFO memory, instead of none in the 16C450, or 16 in the 16C550. The SC16C650A is designed to work with high speed modems and shared network environments that require fast data processing time. Increased performance is realized in the SC16C650A by the larger transmit and receive FIFOs. This allows the external processor to handle more networking tasks within a given time. In addition, the four selectable levels of FIFO trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance, especially when operating in a multi-channel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC16C650A is capable of operation up to 3 Mbits/s with a 48 MHz external clock input (at 5 V). The rich feature set of the SC16C650A is available through internal registers. Automatic hardware/software flow control, selectable transmit and receive FIFO trigger level, selectable TX and RX baud rates, modem interface controls, and a sleep mode are some of these features. IOW, IOW 20, 21 16, 17 18, 19 I Write inputs. When either IOW or IOW is active (LOW or HIGH, respectively) and while the UART is selected, the CPU is allowed to write control words or data into a selected UART register. Only one of these inputs is required to transfer data during a write operation; the other input should be tied to its inactive level (i.e., IOW tied LOW or IOW tied HIGH). XTAL1 18 14 16 I Crystal connection or External clock input. XTAL2[1] 19 15 17 O Crystal connection or the inversion of XTAL1 if XTAL1 is driven. Table 2: Pin description…continued Symbol Pin Type Description PLCC44 LQFP48 DIP40 |
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