M45PE20-VMN6TG datasheet(17/35 Pages) STMICROELECTRONICS

Part #	M45PE20-VMN6TG

Description	2 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 25 MHz SPI Bus Interface

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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M45PE20

Page Write (PW)

The Page Write (PW) instruction allows bytes to

be written in the memory. Before it can be accept-

ed, a Write Enable (WREN) instruction must previ-

ously have been executed. After the Write Enable

(WREN) instruction has been decoded, the device

sets the Write Enable Latch (WEL).

The Page Write (PW) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, three address bytes and at least

one data byte on Serial Data Input (D). The rest of

the page remains unchanged if no power failure

occurs during this write cycle.

The Page Write (PW) instruction performs a page

erase cycle even if only one byte is updated.

If the 8 least significant address bits (A7-A0) are

not all zero, all transmitted data exceeding the ad-

dressed page boundary wrap round, and are writ-

ten from the start address of the same page (the

one whose 8 least significant address bits (A7-A0)

are all zero). Chip Select (S) must be driven Low

for the entire duration of the sequence.

The instruction sequence is shown in Figure 13..

If more than 256 bytes are sent to the device, pre-

viously latched data are discarded and the last 256

data bytes are guaranteed to be written correctly

within the same page. If less than 256 Data bytes

are sent to device, they are correctly written at the

requested addresses without having any effects

on the other bytes of the same page.

Chip Select (S) must be driven High after the

eighth bit of the last data byte has been latched in,

otherwise the Page Write (PW) instruction is not

executed.

As soon as Chip Select (S) is driven High, the self-

timed Page Write cycle (whose duration is tPW) is

initiated. While the Page Write cycle is in progress,

the Status Register may be read to check the val-

ue of the Write In Progress (WIP) bit. The Write In

Progress (WIP) bit is 1 during the self-timed Page

Write cycle, and is 0 when it is completed. At some

unspecified time before the cycle is complete, the

Write Enable Latch (WEL) bit is reset.

A Page Write (PW) instruction applied to a page

that is Hardware Protected is not executed.

Any Page Write (PW) instruction, while an Erase,

Program or Write cycle is in progress, is rejected

without having any effects on the cycle that is in

progress.

Figure 13. Page Write (PW) Instruction Sequence

Note: 1. Address bits A23 to A18 are Don’t Care

2. 1

≤ n ≤ 256

C

D

AI04045

S

42

41

43 44 45 46 47 48 49 50

52 53 54 55

40

C

D

S

23

2

1

3456789 10

28 29 30 31 32 33 34 35

22 21

3210

36 37 38

Instruction

24-Bit Address

0

765432

0

1

Data Byte 1

39

51

765432

0

1

Data Byte 2

765432

0

1

Data Byte 3

Data Byte n

765432

0

1

MSB

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M45PE20-VMN6TG Datasheet(PDF) 17 Page - STMicroelectronics

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