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ISL3873IK Datasheet(PDF) 15 Page - Intersil Corporation |
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ISL3873IK Datasheet(HTML) 15 Page - Intersil Corporation |
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15 / 31 page  15 USB Port The USB interface implemented in the ISL3873 complies with the Universal Serial Bus Specification Revision 1.1. dated September 23, 1998, which is available from the USB Implementers’ Forum at http://www.usb.org/. The USB supports 4 endpoints. • One Communications Class control endpoint for interface management; • One Communications Class interrupt endpoint for signalling interrupts to the host; and, • Two Bulk endpoints for transfer of encapsulated NDIS functions to and from the host. The USB along with USB support firmware provides an alternate host interface for attaching an 802.11{b} WLAN adapter to a host computer. This interface does not provide “wireless USB” where USB packets are sent on the wireless medium due to timing constraints in the USB protocol. USB+ and USB- are the differential pair signals provided for the user. These signals are capable of directly driving a USB cable. USB_DETECT is a 5V tolerant input to the ISL3873 device. It is used to signal the MAC processor that a USB cable is attached to the unit. Complete details on the USB firmware for controlling this port can be obtained by contacting the factory directly. Power Sequencing The ISL3873 provides a number of firmware controlled port pins that are used for controlling the power sequencing and other functions in the front end components of the radio. Packet transmission requires precise control of the radio. Ideally, energy at the antenna ceases after the last symbol of information has been transmitted. Additionally, the transmit/receive switch must be controlled properly to protect the receiver. It's also important to apply appropriate modulation to the PA while it's active. Signaling sequences for the beginning and end of normal transmissions are illustrated in Figure 10. Table 1 lists applicable delays associated with these control signals. A transmission begins with PE2 as shown in Figure 10. Next, the transmit/receive switch is configured for transmission via the differential pair TR_SW and TR_SW_BAR. This is followed by a transmit enable (TX_ENABLE) to the Baseband processor inside the ISL3873. This enable activates the transmit state machine in the BBP. Lastly, PA_PE activates the PA. Delays for these signals related to the initiation of transmission are referenced to PE2. Immediately after the final data bit has been clocked out of the MAC the Baseband processor is disabled. The MAC then waits for a control signal (TX_READY) from the Baseband processor to go inactive, signaling that the BBP has modulated the final information-rich symbol. It then immediately de-asserts PA_PE followed by placing the transmit/receive switch in the receive position and ending with PE2 going high. Delays for these signals related to the termination of transmission are referenced to the rising edge of PE2 . PE1 and PE2 encoding details are found in Table 2. Note that during normal receive and transmit operation that PE1 is static and PE2 toggles for receive and transmit states. FIGURE 9. BLOCK DIAGRAM OF A BUFFER ACCESS PATH BUFFER DESCRIPTOR ACCESS (FIRMWARE) ALLOCATE/ DEALLOCATE REQUEST BLOCK OFFSET VIRTUAL FRAME BUFFER DATA PORT PRE-READ/ POST-WRITE OFFSET CENTER HOST BUS STATUS HEADER DATA BUFFER MEMORY A FID D TABLE 1. TRANSMIT CONTROL TIMING SPECIFICATIONS PARAMETER SYMBOL DELAY TOLERANCE UNITS PE2 to TR Switch tD1 2 ±0.1 µs PE2 to PA_PE tD3 3 ±0.1 µs PA_PE to PE2 tD4 3 ±0.1 µs TR Switch to PE2 tD5 2 ±0.1 µs ISL3873 |
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