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IS24C52-3G Datasheet(PDF) 3 Page - Integrated Silicon Solution, Inc

Part # IS24C52-3G
Description  2k-bit 2-WIRE SERIAL CMOS EEPROM with Permanent Write-Protection
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS24C52-3G Datasheet(HTML) 3 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
3
PRELIMINARYINFORMATION
Rev.00B
01/26/04
IS24C52
ISSI®
PIN DESCRIPTIONS
A0-A2
Address Inputs
SDA
Serial Address/Data I/O
SCL
Serial Clock Input
WP
Write Protect Input
Vcc
Power Supply
GND
Ground
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wire Or'ed with other open drain or
open collector outputs. The SDA bus
requires a pullup
resistor to Vcc.
PIN CONFIGURATION
8-Pin SOIC, TSSOP, MSOP
WP
WP is the Write Protect pin. If the WP pin is tied to Vcc, the
entire array becomes Write Protected, and software write-
protection cannot be initiated. When WP is tied to GND or
left floating, normal read/write operations are allowed to the
device. If the device has already received a write-protection
command, the memory in the range of 00h-7Fh is read -only
regardless of the setting of the WP pin.
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
A0, A1, A2
The A0, A1, and A2 are the device address inputs that are
hardwired or left unconnected for hardware flexibility. When
pins are hardwired, as many as eight devices may be
addressed on a single bus system. When the pins are not
hardwired, the default A0, A1, and A2 are zero.
DEVICE OPERATION
The IS24C52 features a serial communication and supports
a bi-directional 2-wire bus transmission protocol.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the
receiving devices as a receiver. The bus is controlled by
Master device which generates the SCL, controls the bus
access and generates the Stop and Start conditions. The
IS24C52 is the Slave device on the bus.


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