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ISL3873 Datasheet(PDF) 20 Page - Intersil Corporation

Part No. ISL3873
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL3873 Datasheet(HTML) 20 Page - Intersil Corporation

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Header Field
The header field is defined by four fields which are shown in
Figure 14. These fields are Signal Field, Service Field,
Length Field and CITT-CRC16 Field. They are further
defined by the following:
Signal Field (8 Bits) - This field indicates what data rate the
data packet that follows the header will be. The ISL3873
receiver looks at the signal field to determine whether it
needs to switch from DBPSK demodulation into DQPSK, or
CCK demodulation at the end of the preamble and header
fields.
Service Field (8 Bits) - The MSB of this field is used to
indicate the correct length when the length field value is
ambiguous at 11Mbps. See IEEE STD 802.11 for definition
of the other bits. Bit 2 is used by the ISL3873 to indicate that
the carrier reference and the bit timing references are
derived from the same oscillator (locked oscillators).
Length Field (16 Bits) - This field indicates the number of
microseconds it will take to transmit the payload data
(PSDU). The external controller (MAC) will check the length
field in determining when it needs to de-assert RX_PE.
CCITT - CRC 16 Field (16 Bits) - This field includes the
16-bit CCITT - CRC 16 calculation of the three header fields.
This value is compared with the CCITT - CRC 16 code
calculated at the receiver. The ISL3873 receiver will indicate
a CCITT - CRC 16 error via CR24 bit 2 and will lower
MD_RDY and reset the receiver to the acquisition mode if
there is an error.
The CRC or cyclic Redundancy Check is a CCITT CRC-16
FCS (Frame Check Sequence). It is the ones complement of
the remainder generated by the modulo 2 division of the
protected bits by the polynomial:
x16 + x12 + x5 + 1
The protected bits are processed in transmit order. All CRC
calculations are made ahead of data scrambling. A shift
register with two taps is used for the calculation. It is preset
to all ones and then the protected fields are shifted through
the register. The output is then complemented and the
residual shifted out MSB first.
The following Configuration Registers (CR) are used to
program the preamble/header functions, more programming
details about these registers can be found in the Control
Registers section of this document:
802.11 DSSS BPSK
802.11 DSSS QPSK
1Mbps
BARKER
2Mbps
BARKER
DATA
IOUT
QOUT
CHIP
RATE
1 BIT ENCODED TO
2 BITS ENCODED
4 CODE WORDS
SYMBOL
RATE
I vs. Q
11 MC/S
11 MC/S
1 MS/S
1 MS/S
11 CHIPS
11 CHIPS
TO ONE OF
FIGURE 13. MODULATION MODES
ONE OF 2 CODE
WORDS
(TRUE-INVERSE)
5.5Mbps CCK
4 BITS ENCODED
11 MC/S
1.375 MS/S
8 CHIPS
COMPLEX
SPREAD FUNCTIONS
TO ONE OF 16
COMPLEX CCK
CODE WORDS
11Mbps CCK
8 BITS ENCODED
11 MC/S
1.375 MS/S
8 CHIPS
COMPLEX
SPREAD FUNCTIONS
TO ONE OF 256
COMPLEX CCK
CODE WORDS
PREAMBLE (SYNC)
128/56 BITS
Start FRAME DELIMITER
16 BITS
SIGNAL FIELD
8 BITS
SERVICE FIELD
8 BITS
LENGTH FIELD
16 BITS
CRC16
16 BITS
HEADER
PREAMBLE
FIGURE 14. 802.11 PREAMBLE/HEADER
ISL3873


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