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ISL3873 Datasheet(PDF) 13 Page - Intersil Corporation

Part No. ISL3873
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL3873 Datasheet(HTML) 13 Page - Intersil Corporation

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For 8-bit spaces, the ISL3873 dynamically configures pin
MUBE-/MA0/MWEH- cycle-by-cycle as the address LSB.
MWEL-/MWE- is the only write control, and MOE- is the read
output enable.
For 16-bit spaces constructed from 8-bit memories, the
ISL3873 dynamically configures pin MUBE-/MA0/MWEH-
cycle-by-cycle as the high byte write enable, MWEL- as the low
write enable signal, and MOE- as the read output enable.
For 16-bit spaces constructed from single-chip x16
memories (such as SRAMs), the ISL3873 dynamically
configures pin MUBE_/MA0/MWEH- cycle-by-cycle as the
upper byte enable. Pin MLBE- is connected as the low byte
enable, MWEL-/MWE- is the write control, and MOE- is the
read output enable.
These memory implementations require no external logic.
The memory spaces may each be constructed from any type
of memory desired. The only restriction is that a single
memory space must be constructed from the same type of
memory; for example, data space may not use both x8 and
x16 memories, it must be all x8, or all x16. This restriction
does not apply across memory spaces; e.g., code space may
use a x8 memory and data space a single x16 memory, or
code space two x8 memories and data space a single x8
Serial EEPROM Interface
The ISL3873 contains a small on-chip ROM firmware which
was added to allow the CIS or CIS plus firmware image to be
transferred from an off-chip serial non-volatile memory device
to RAM after a system reset. This allows a system configuration
without a parallel Flash device. The operating frequency of the
serial port is 400kHz with a voltage of 3.3V. Refer to Figure 8 for
additional details on configuring the serial memory to the
ISL3873. The Power On Reset Configuration section in this
document provides additional details on memory selection and
control after a Reset condition.
PC Card Interface
PC Card Physical Interface
The Host interface is compatible to the PC Card 95 Standard
(PCMCIA v2.1). The ISL3873 Host Interface pins connect
directly to the correspondingly named pins on the PC Card
connector with no external components (other than resistors)
required. The ISL3873 operates as an I/O card using less
than 64 octet locations. Reads and writes to internal registers
and buffer memory are performed by I/O accesses. Attribute
memory (256 octets) is provided for the CIS table which is
located in external memory. Common memory is not used.
The following describes specific features of various pins:
Decoding of the system address space is performed by the
HCEx-. During I/O accesses HA[5:0] decode the register.
HA[9:6] are ignored when the internal HAMASK register is
set to the defaults used by the standard firmware. During
attribute memory accesses HA[9:1] are used.
The host interface is primarily designed for word accesses,
although all byte access modes are fully supported. See
HCE1-, HCE2- for a further description. Note that attribute
memory is specified for and operates with even bytes accesses
HCE1-, HCE2-
The PC Card cycle type and width are controlled with the CE
signals. Word and Byte wide accesses are supported, using
the combinations of HCE1-, HCE2-, and HA0 as specified in
the PC Card standard.
HOE- and HWE- are only used to access attribute memory.
Common Memory, as specified in the PC Card standard, is
not used in the ISL3873. HOE- is the strobe that enables an
attribute memory read cycle. HWE- is the corresponding
strobe for the attribute memory write cycle. The attribute
space contains the Card Information Structure (CIS) as well
as the Function Configuration Registers (FCR).
HIORD- and HIOWR- are the enabling strobes for register
access cycles to the ISL3873. These cycles can only be
performed once the initialization procedure is complete and
the ISL3873 has been put into IO mode.
This signal must be asserted for I/O or attribute cycles. A
cycle where HREG- is not asserted will be ignored as the
ISL3873 does not support common memory.
This signal is asserted by the ISL3873 whenever a valid I/O
read cycle takes place. A valid cycle is when HCE1-, HCE2-,
HREG-, and HIORD- are asserted, once the initialization
procedure is complete.
Wait states are inserted in accesses using HWAIT-. The host
interface synchronizes all PC Card cycles to the internal
ISL3873 clock. The following wait states should be expected:
Direct Read or Write to Hardware Register
• 1/2 to 1 MCLK assertion of HWAIT- for internal
Write to Memory Mapped Register, Buffer Access Path,
or Attribute Space (Post-Write)
• The data required for the write cycle will be latched and
therefore only the synchronizing wait state will occur.
• Until the queued cycle has actually written to the memory,
any subsequent access by the Host will result in a WAIT.

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