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ISL3873 Datasheet(PDF) 29 Page - Intersil Corporation

Part No. ISL3873
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL3873 Datasheet(HTML) 29 Page - Intersil Corporation

 
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29
Demodulator Performance
This section indicates the typical performance measures for
a radio design. The performance data below should be used
as a guide. In general, the actual performance depends on
the application, interference environment, RF/IF
implementation and radio component selection.
Overall Eb/N0 Versus BER Performance
The PRISM chip set has been designed to be robust and
energy efficient in packet mode communications. The
demodulator uses coherent processing for data
demodulation. The figures below show the performance of
the baseband processor when used in conjunction with the
HFA3783 IF and the PRISM recommended IF filters. Off the
shelf test equipment are used for the RF processing. The
curves should be used as a guide to assess performance in
a complete implementation.
Factors for carrier phase noise, multipath, and other
degradations will need to be considered on an
implementation by implementation basis in order to predict
the overall performance of each individual system.
Figure 18 shows the curves for theoretical DBPSK/DQPSK
demodulation with coherent demodulation and
descrambling as well as the PRISM performance measured
for DBPSK and DQPSK. The theoretical performance for
DBPSK and DQPSK are the same as shown on the
diagram. Figure 21 shows the theoretical and actual
performance of the CCK modes. The losses in both figures
include RF and IF radio losses; they do not reflect the
ISL3873 losses alone. The ISL3873 baseband processing
losses from theoretical are, by themselves, a small
percentage of the overall loss.
The PRISM demodulator performs with an implementation
loss of less than 4dB from theoretical in a AWGN
environment with low phase noise local oscillators. For the
1 and 2Mbps modes, the observed errors occurred in
groups of 4 and 6 errors. This is because of the error
extension properties of differential decoding and
descrambling. For the 5.5 and 11Mbps modes, the errors
occur in symbols of 4 or 8 bits each and are further
extended by the descrambling. Therefore the error patterns
are less well defined.
Clock Offset Tracking Performance
The PRISM baseband processor is designed to accept data
clock offsets of up to
±25ppm for each end of the link (TX
and RX). This effects both the acquisition and the tracking
performance of the demodulator. The budget for clock offset
error is 0.75dB at
±50ppm. No appreciable degradation was
seen for operation in AWGN at
±50ppm. Symbol tracking is
accomplished by one of two methods. If both ends of the link
employ locked oscillators for their bit timing and carrier
frequency generation, symbol tracking is done by dividing
down the carrier frequency offset. If either one of the ends of
the link do not have locked oscillators, then symbol tracking
is done by a conventional early-late chip tracking method.
Carrier Offset Frequency Performance
The correlators used for acquisition for all modes and for
demodulation in the 1 and 2Mbps modes are time invariant
matched filter correlators otherwise known as parallel
correlators. They use two samples per chip and are tapped
at every other shift register stage. Their performance with
carrier frequency offsets is determined by the phase roll rate
due to the offset. For an offset of +50ppm (combined for both
TX and RX) will cause the carrier to phase roll 22.5 degrees
over the length of the correlator. This causes a loss of
0.22dB in correlation magnitude which translates directly to
Eb/N0 performance loss. In the PRISM chip design, the
carrier phase locked loop is inactive during acquisition.
During tracking, the carrier tracking loop corrects for offset,
so that no degradation is noted. In the presence of high
multipath and high SNR, however, some degradation is
expected.
FIGURE 20. BER vs Eb/N0 PERFORMANCE FOR PSK MODES
FIGURE 21. BER vs Eb/N0 PERFORMANCE FOR CCK MODES
78
9
10
11
12
Eb/N0
1.E+00
1.E-03
1.E-04
1.E-05
1.E-07
1.E-08
1.E-02
1.E-06
1.E-01
BER 1.0
THY 1, 2
BER 2.0
14
13
12
11
10
9
8
7
6
5
Eb/N0
1.E+00
1.E-03
1.E-04
1.E-05
1.E-07
1.E-08
1.E-02
1.E-06
1.E-01
1.E-09
BER 11
BER 5.5
THY 5.5
THY 11
ISL3873


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