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IS24C52-2G Datasheet(PDF) 5 Page - Integrated Silicon Solution, Inc |
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IS24C52-2G Datasheet(HTML) 5 Page - Integrated Silicon Solution, Inc |
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5 / 14 page  Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5 PRELIMINARYINFORMATION Rev.00B 01/26/04 IS24C52 ISSI® WRITE OPERATION Byte Write In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/ W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends a byte address that is written into the address pointer of the IS24C52. After receiving another ACK from the Slave, the Master device transmits the data byte to be written into the address memory location. The IS24C52acknowledgesoncemoreandtheMastergenerates the Stop condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device. Page Write The IS24C52 is capable of 16-byte Page-Write operation. A Page-Write is initiated in the same manner as a Byte Write, but instead of terminating the internal Write cycle after the first data byte is transferred, the Master device can transmit up to 15 more bytes. After the receipt of each data byte, the IS24C52 responds immediately with an ACK on SDA line, and the four lower order data byte address bits are internally incremented by one, while the higher order bits of the data byte address remain constant. If a byte address is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device should transmit more than 16 bytes prior to issuing the Stop condition, the address counter will “roll over,” and the previously written data will be overwritten. Once all 16 bytes are received and the Stop condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the IS24C52 in a single Write cycle. All inputs are disabled until completion of the internal Write cycle. Acknowledge (ACK) Polling The disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the Stop condition is issued to indicate the end of the host's Write operation, the IS24C52 initiates the internal Write cycle. ACK polling can be initiated immediately. This involves issuing the Start condition followed by the Slave address for a Write operation. If the IS24C52 is still busy with the Write operation, no ACK will be returned. If the IS24C52 has completed the Write operation, an ACK will be returned and the host can then proceed with the next Read or Write operation. Permanent Write Protection The IS24C52 contains a permanent write protection feature that is initiated by means of a software command. After the command is transmitted, the protected area becomes irreversibly read-only despite power removal and re- application on the device. The address range of the 128 bytes of the array that is affected by this feature is 00h-7Fh. Once enabled, the permanent protection is independent of the status of the WP pin. (If WP is raised to High, the entire array is read-only. If WP is low, the region 00h-7Fh can still be read-only.) The software command is initiated similarly to a normal byte write operation; however, the slave address begins with the bits 0110 (see Figure 5). The following three bits are A2 - A0. The last bit of the slave address (R/ W) is 0. If the IS24C52 responds with ACK, then the device has not yet had its write-protection permanently enabled. To complete the command, the Master must transmit a dummy address byte, dummy data byte, and a Stop signal (see Figure 11). The WP pin must be Low during this command. Before resuming any other command, the internal write cycle should be observed. The status of the permanent write protection can be safely determined without any changes by transmitting the same Slave address as above, but with the last bit (R/ W) set to 1(see Figure 12). If the permanent write protection has been enabled, then the IS24C52 will not acknowledge any slave address starting with bits 0110 (see Figure 5). |
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