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CY28329 Datasheet(PDF) 8 Page - Cypress Semiconductor

Part No. CY28329
Description  133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28329 Datasheet(HTML) 8 Page - Cypress Semiconductor

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CY28329
Document #: 38-07040 Rev. *E
Page 8 of 17
Switching Characteristics Over the Operating Range[8]
Parameter
Output
Description
Test Conditions
Min.
Max.
Unit
t1
All
Output Duty Cycle[9]
Measured at 1.5V
45
55
%
t2
CPU
Rise Time
Measured differential waveform from
–0.35V to +0.35V
175
700
ns
t2
USB, REF,
DOT
Rising Edge Rate
Between 0.4V and 2.4V
0.5
2.0
ns
t2
PCI, 3V66
Rising Edge Rate
Between 0.4V and 2.4V
1.0
4.0
V/ns
t3
CPU
Fall Time
Measured differential waveform from
–0.35V to +0.35V
175
700
ps
t3
USB, REF,
DOT
Falling Edge Rate
Between 2.4V and 0.4V
0.5
2.0
ns
t3
PCI, 3V66
Falling Edge Rate
Between 2.4V and 0.4V
1.0
4.0
V/ns
t4
CPU
CPU-CPU Skew
Measured at Crossover
150
ps
t5
3V66 [0:1]
3V66-3V66 Skew
Measured at 1.5V
500
ps
t5
66BUFF[0:2]
66BUFF-66BUFF Skew
Measured at 1.5V
175
ps
t6
PCI
PCI-PCI Skew
Measured at 1.5V
500
ps
t7
3V66, PCI
3V66-PCI Clock Skew
3V66 leads. Measured at 1.5V
1.5
3.5
ns
t8
CPU
Cycle-Cycle Clock Jitter
Measured at Crossover t8 = t8A – t8B
With all outputs running
150
ps
t9
3V66
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
250
ps
t9
USB, DOT
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
350
ps
t9
PCI
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
500
ps
t9
REF
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
1000
ps
t10
ALL
POR timing
Measured at 1.5V[10, 11]
1.0
4.0
ms
CPU
Rise/Fall Matching
Measured with test loads[12, 13]
235
mV
Voh
CPU
High-level Output Voltage
including overshoot
Measured with test loads[13]
0.92
1.45
V
Vol
CPU
Low-level Output Voltage
including undershoot
Measured with test loads[13]
–0.2
0.35
V
Vcrossover
CPU
Crossover Voltage
Measured with test loads[13]
0.250
0.550
V
Notes:
8. All parameters specified with loaded outputs.
9. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
10. POR starts when VDD reaches 1.5V.
11. All PULL-UPs must ramp at the same rate as VDD.
12. Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trn is an intersecting falling edge.
13. The test load is Rs = 33.2Ω, Rp = 49.9Ω in test circuit.


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