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ADCLK946 Datasheet(PDF) 1 Page - Analog Devices

Part # ADCLK946
Description  Six LVPECL Outputs, SiGe Clock Fanout Buffer
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADCLK946 Datasheet(HTML) 1 Page - Analog Devices

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Six LVPECL Outputs,
SiGe Clock Fanout Buffer
Data Sheet
ADCLK946
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2009–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
4.8 GHz operating frequency
75 fs rms broadband random jitter
On-chip input terminations
3.3 V power supply
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
GENERAL DESCRIPTION
The ADCLK946 is an ultrafast clock fanout buffer fabricated on
the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The device has a differential input equipped with center-tapped,
differential, 100 Ω on-chip termination resistors. The input accepts
dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and
ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin
is available for biasing ac-coupled inputs.
The ADCLK946 features six full-swing emitter-coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias VCC to the positive supply and VEE to ground. For ECL
operation, bias VCC to ground and VEE to the negative supply.
The ECL output stages are designed to directly drive 800 mV
each side into 50 Ω terminated to VCC − 2 V for a total differen-
tial output swing of 1.6 V.
The ADCLK946 is available in a 24-lead LFCSP and is specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
LVPECL
CLK
VT
VREF
CLK
ADCLK946
REFERENCE
Figure 1.


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