EP

BIAS

GATE

VCC

PGND

CS

COMP

PGOOD

UVLO/SYNC

SS

RT

FB

AGND

1

2

3

4

5

6

12

11

10

9

8

7

4

LM5155-Q1

SNVSB00 – AUGUST 2018

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(1)

G = Ground, I = Input, O = Output, P = Power

7 Pin Configuration and Functions

DSS Package

12-Pin WSON With Wettable Flanks

Top View

Pin Functions

PIN

DESCRIPTION

NO.

NAME

1

BIAS

P

Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to PGND

2

VCC

P

Output of the internal VCC regulator and supply voltage input of the MOSFET driver. Connect a ceramic

bypass capacitor from this pin to PGND.

3

GATE

O

N-channel MOSFET gate drive output. Connect directly to the gate of the N-channel MOSFET through

a short, low inductance path.

4

PGND

G

Power ground pin. Connect directly to the ground connection of the sense resistor through a low

inductance wide and short path.

5

CS

I

Current sense input pin. Connect to the positive side of the current sense resistor through a short path.

6

COMP

O

Output of the internal transconductance error amplifier. Connect the loop compensation components

between this pin and PGND.

7

AGND

G

Analog ground pin. Connect to the analog ground plane through a wide and short path.

8

FB

I

Inverting input of the error amplifier. Connect a voltage divider from the output to this pin to set output

voltage in boost/SEPIC topologies. Connect the low-side feedback resistor to AGND.

9

SS

I

Soft-start time programming pin. An external capacitor and an internal current source set the ramp rate

of the internal error amplifier reference during soft-start. Connect the ground connection of the capacitor

to AGND.

10

RT

I

Switching frequency setting pin. The switching frequency is programmed by a single resistor between

RT and AGND.

11

PGOOD

O

Power-good indicator. An open-drain output which goes low if FB is below the under voltage threshold.

Connect a pullup resistor to the system voltage rail.

12

UVLO/SYNC

I

Under voltage lockout programming pin. The converter start-up and shutdown levels can be

programmed by connecting this pin to the supply voltage through a resistor divider. The internal clock

can be synchronized to an external clock by applying a negative pulse signal into the UVLO/SYNC pin.

This pin should not be left floating. Connect to BIAS pin if not used. Connect the low-side UVLO resistor

to AGND.

—

EP

—

Exposed pad of the package. No internal electrical connection to silicon die. The exposed pad must be

connected to AGND and the large ground copper plain to decrease thermal resistance.