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MC9S08PL60 Datasheet(PDF) 19 Page - NXP Semiconductors

Part No. MC9S08PL60
Description  8-Bit S08 central processor unit
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MC9S08PL60 Datasheet(HTML) 19 Page - NXP Semiconductors

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6.2 NVM specifications
This section provides details about program/erase times and program/erase endurance for
the flash and EEPROM memories.
Table 11. Flash characteristics
C
Characteristic
Symbol
Min1
Typical2
Max3
Unit4
D
Supply voltage for program/erase -40 °C
to 85 °C
Vprog/erase
2.7
5.5
V
D
Supply voltage for read operation
VRead
2.7
5.5
V
D
NVM Bus frequency
fNVMBUS
1
25
MHz
D
NVM Operating frequency
fNVMOP
0.8
1
1.05
MHz
D
Erase Verify All Blocks
tVFYALL
17338
tcyc
D
Erase Verify Flash Block
tRD1BLK
16913
tcyc
D
Erase Verify EEPROM Block
tRD1BLK
810
tcyc
D
Erase Verify Flash Section
tRD1SEC
484
tcyc
D
Erase Verify EEPROM Section
tDRD1SEC
555
tcyc
D
Read Once
tRDONCE
450
tcyc
D
Program Flash (2 word)
tPGM2
0.12
0.12
0.29
ms
D
Program Flash (4 word)
tPGM4
0.20
0.21
0.46
ms
D
Program Once
tPGMONCE
0.20
0.21
0.21
ms
D
Program EEPROM (1 Byte)
tDPGM1
0.10
0.10
0.27
ms
D
Program EEPROM (2 Byte)
tDPGM2
0.17
0.18
0.43
ms
D
Program EEPROM (3 Byte)
tDPGM3
0.25
0.26
0.60
ms
D
Program EEPROM (4 Byte)
tDPGM4
0.32
0.33
0.77
ms
D
Erase All Blocks
tERSALL
96.01
100.78
101.49
ms
D
Erase Flash Block
tERSBLK
95.98
100.75
101.44
ms
D
Erase Flash Sector
tERSPG
19.10
20.05
20.08
ms
D
Erase EEPROM Sector
tDERSPG
4.81
5.05
20.57
ms
D
Unsecure Flash
tUNSECU
96.01
100.78
101.48
ms
D
Verify Backdoor Access Key
tVFYKEY
464
tcyc
D
Set User Margin Level
tMLOADU
407
tcyc
C
FLASH Program/erase endurance TL to
TH = -40 °C to 85 °C
nFLPE
10 k
100 k
Cycles
C
EEPROM Program/erase endurance TL
to TH = -40 °C to 85 °C
nFLPE
50 k
500 k
Cycles
C
Data retention at an average junction
temperature of TJavg = 85°C after up to
10,000 program/erase cycles
tD_ret
15
100
years
1. Minimum times are based on maximum fNVMOP and maximum fNVMBUS
2. Typical times are based on typical fNVMOP and maximum fNVMBUS
3. Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging
4. tcyc = 1 / fNVMBUS
Peripheral operating requirements and behaviors
MC9S08PL60 Series Data Sheet, Rev. 1, 04/2018
NXP Semiconductors
19


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