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8533AG-01LF Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. 8533AG-01LF
Description  Different ial-to-3.3V LVPECL Fanout Buffer
Download  17 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

8533AG-01LF Datasheet(HTML) 6 Page - Integrated Device Technology

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8533-01 Data Sheet
©2016 Integrated Device Technology, Inc
Revision F January 19, 2016
6
ADDITIVE PHASE JITTER
Input/Output Additive Phase Jit-
ter at 156.25MHz = 0.06ps (typical)
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The spectral purity in a band at a specific offset from the fun-
damental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using
a Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in the
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher
than the noise floor of the device. This is illustrated above. The
1Hz band to the power in the fundamental. When the required
offset is specified, the phase noise is called a dBc value, which
simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
device meets the noise floor of what is shown, but can actually
be lower.The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)


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