8533AG-01LN datasheet(5/17 Pages) IDT | Different ial-to-3.3V LVPECL Fanout Buffer

Part #	8533AG-01LN

Description	Different ial-to-3.3V LVPECL Fanout Buffer

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Manufacturer	IDT [Integrated Device Technology]

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8533-01 Data Sheet

Revision F January 19, 2016

5

TABLE 4D. LVPECL DC CHARACTERISTICS, V

CC = 3.3V±5%, T

A

= 0°C TO 70°C

TABLE 5. AC CHARACTERISTICS, V

CC = 3.3V±5%, T

A

= 0°C TO 70°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

I

IH

Input High Current

PCLK

V

CC = VIN = 3.465V

150

µA

nPCLK

V

CC = VIN = 3.465V

5

µA

I

IL

Input Low Current

PCLK

V

CC = 3.465V, VIN = 0V

-5

µA

nPCLK

V

CC = 3.465V, VIN = 0V

-150

µA

V

PP

Peak-to-Peak Input Voltage

0.3

1

V

CMR

Common Mode Input Voltage; NOTE 1, 2

V

EE + 1.5

V

CC

V

OH

Output High Voltage; NOTE 3

V

CC - 1.4

V

CC - 0.9

V

OL

Output Low Voltage; NOTE 3

V

CC - 2.0

V

CC - 1.7

V

SWING

Peak-to-Peak Output Voltage Swing

0.6

1.0

V

NOTE 1: Common mode voltage is deﬁned as V

IH.

NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is V

CC + 0.3V.

NOTE 3: Outputs terminated with 50Ω to V

CC - 2V.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f

MAX

Output Frequency

650

MHz

t

PD

Propagation Delay; NOTE 1

ƒ ≤ 650MHz

1.0

1.4

ns

tsk(o)

Output Skew; NOTE 2, 4

30

ps

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

150

ps

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter section,

NOTE 5

0.06

ps

t

R / tF

Output Rise/Fall Time

20% to 80% @ 50MHz

300

700

ps

odc

Output Duty Cycle

47

53

%

All parameters measured at 500MHz unless noted otherwise.

The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Deﬁned as skew between outputs at the same supply voltage and with equal load conditions.

Measured at output differential cross points.

NOTE 3: Deﬁned as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at the differential cross points.

NOTE 4: This parameter is deﬁned in accordance with JEDEC Standard 65.

NOTE 5: Driving only one input clock.

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