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LMX2323 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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LMX2323 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
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11 / 12 page  2.0 Programming Description (Continued) 2. Both synchronous and asynchronous power down modes are available with the LMX2323 to be able to adapt to different types of applications. The MICROWIRE control register remains active and capable of loading and latching in data during all of the powerdown modes. Synchronous Power down Mode The PLL loops can be synchronously powered down by setting the counter reset mode bit to LOW (N[2] = 0) and its power down mode bit to HIGH (N[1] = 1). The power down function is gated by the charge pump. Once the power down mode and counter reset mode bits are loaded, the part will go into power down mode upon the completion of a charge pump pulse event. Asynchronous Power down Mode The PLL loops can be asynchronously powered down by setting the counter reset mode bit to HIGH (N[2] = 1) and its power down mode bit to HIGH (N[1] = 1). The power down function is NOT gated by the charge pump. Once the power down and counter reset mode bits are loaded, the part will go into power down mode immediately. The R and N counters are disabled and held at load point during the synchronous and asynchronous power down modes. This will allow a smooth acquisition of the RF signal when the PLL is programmed to power up. Upon powering up, both R and N counters will start at the ‘zero’ state, and the relationship between R and N will not be random. Serial Data Input Timing Phase Comparator and Internal Charge Pump Characteristics DS101362-6 Notes: Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6 V/ns with amplitudes of 2.2V @ VCC = 2.7V and 2.6V @ VCC = 5.5V. DS101362-7 Notes: Phase difference detection range: −2 π to +2π The minimum width pump up and pump down current pulses occur at the CPo pin when the loop is locked. PD_POL = 1 fr: Phase comparator input from the R divider fp: Phase comparator input from the N divider CPo: Charge pump output www.national.com 11 |
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