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LMX2323 Datasheet(PDF) 10 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. LMX2323
Description  PLLatinum 2.0 GHz Frequency Synthesizer for RF Personal Communications
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LMX2323 Datasheet(HTML) 10 Page - National Semiconductor (TI)

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2.0 Programming Description (Continued)
2.3.1 5-Bit Swallow Counter Divide Ratio (A Counter)
Swallow Count
NA_CNTR
(A)
43210
0
00000
1
00001
•••••
31
11111
Notes: Swallow Counter Value: 0 to 31
NB_CNTR
≥ NA_CNTR
2.3.2 10-Bit Programmable Counter Divide Ratio (B Counter)
NB_CNTR
Divide Ratio
9876543210
3
0000000011
4
0000000100
••••••••••
1023
1111111111
Notes: Divide ratio: 3 to 1,023 (Divide ratios less than 3 are prohibited).
NB_CNTR
≥ NA_CNTR
2.3.3 Pulse Swallow Function
The N divider counts such that it divides the VCO RF frequency by (P+1) A times, and then divides by P (B - A) times. The B value
(NB_CNTR) must be
≥ 3. The continuous divider ratio is from 992 to 32,767. Divider ratios less than 992 are achievable as long
as the binary counter value is greater than the swallow counter value (NB_CNTR
≥ NA_CNTR).
f
VCO =Nx(fOSC/R)
N=(P x B) + A
f
VCO:
Output frequency of external voltage controlled oscillator (VCO)
f
OSC:
Output frequency of the external reference frequency oscillator
R:
Preset divide ratio of binary 10-bit programmable reference counter (2 to 1023)
N:
Preset divide ratio of main 15-bit programmable integer N counter (992 to 32,767)
B:
Preset divide ratio of binary 10-bit programmable B counter (3 to 1023)
A:
Preset value of binary 5-bit swallow A counter (0
≤ A ≤ 31, A ≤ B)
P:
Preset modulus of dual modulus prescaler (P = 32)
2.3.4 CTL_WORD
MSB
LSB
N2
N1
CNT_RST
PWDN
2.3.4.1 Reserve Word Truth Table
CE
CNT_RST
PWDN
Function
1
0
0
Normal Operation
1
0
1
Synchronous Powerdown
1
1
0
Counter Reset
1
1
1
Asynchronous Powerdown
0
X
X
Asynchronous Powerdown
Notes: X denotes don’t care.
1.
The Counter Reset bit when activated allows the reset of both N and R counters. Upon powering up the N counter resumes
counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle).
www.national.com
10


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