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LMX2323 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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LMX2323 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
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7 / 12 page  2.0 Programming Description 2.1 MICROWIRE INTERFACE The MICROWIRE interface is comprised of an 18-bit shift register, a R register and a N register. The shift register consists of a 17-bit DATA field and a 1-bit address (ADDR) field as shown below. When Latch Enable transitions HIGH, data stored in the shift register is loaded into either the R or N register depending on the ADDR bit as described in Table 2.1.1. The data is loaded MSB first. The DATA field assignment for the R and N registers are shown in Table 2.1.2 below. MSB LSB DATA [16:0] ADDR 17 1 0 2.1.1 Address Bit Truth Table When LE is transitioned high, data is transferred from the 18-bit shift register into either the 14-bit R register, or the 17-bit N register depending upon the state of the ADDR bit. ADDR DATA Location 0 N register 1 R register 2.1.2 Register Content Truth Table MSB SHIFT REGISTER BIT LOCATION LSB 17 16 15 14 13 12 11 10 9 8 7654 3 2 1 0 N Register NB_CNTR NA_CNTR CTL_WORD 0 R Register X X LD_OUT PD_POL CP_TRI R_CNTR 1 2.2 R REGISTER If the Address Bit (ADDR) is 1, when LE is transitioned high data is transferred from the 18-bit shift register into the 14-bit R register. The R register contains a latch which sets the PLL 10-bit R counter divide ratio. The divide ratio is programmed using the bits R_CNTR as shown in 2.2.1 10-Bit Programmable Reference Divider Ratio (R Counter). The ratio must be ≥ 2. The PD_POL and CP_TRI bits control the phase detector polarity and charge pump TRI-STATE respectively, as shown in 2.2.2 R[11], R[12] Truth Table. X denotes a don’t care condition. First Bit SHIFT REGISTER BIT LOCATION Last Bit 17 16 15 14 13 12 11 10987654 3210 X X LD_OUT PD_POL CP_TRI R_CNTR [9:0] 1 2.2.1 10-Bit Programmable Reference Divider Ratio (R Counter) R_CNTR Divide Ratio 9876543210 2 0000000010 3 0000000011 • •••••••••• 1,023 1111111111 Note: Divide ratio: 2 to 1,023 (Divide ratios less than 2 are prohibited). R_CNTR — These bits select the divide ratio of the programmable reference dividers. 2.2.2 R[11], R[12] Truth Table Bit Location Function 0 1 CP_TRI R[11] Charge Pump TRI-STATE Normal Operation TRI-STATE PD_POL R[12] Phase Detector Polarity Negative Positive Note: Depending upon VCO characteristics, R[12] shoud be set accordingly. When VCO characteristics are positive, R[12] should be set HIGH. When VCO characteristics are negative, R[12] should be set LOW. www.national.com 7 |
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