LMX2323 datasheet(6/12 Pages) NSC | PLLatinum 2.0 GHz Frequency Synthesizer for RF Personal Communications

6 / 12 page

1.0 Functional Description

The basic phase-lock-loop (PLL) configuration consists of a

high-stability crystal reference oscillator, a frequency synthe-

sizer such as the National Semiconductor LMX2323, a volt-

age controlled oscillator (VCO), and a passive loop filter. The

frequency synthesizer includes a phase detector, current

mode charge pump, as well as programmable reference [R]

and feedback [N] frequency dividers. The VCO frequency is

established by dividing the crystal reference signal down via

the R counter to obtain a frequency that sets the comparison

frequency. This reference signal, f

r, is then presented to the

input of a phase/frequency detector and compared with an-

other signal, f

p, the feedback signal, which was obtained by

dividing the VCO frequency down by way of the N counter.

The phase/frequency detector’s current source outputs

pump charge into the loop filter, which then converts the

charge into the VCO’s control voltage. The phase/frequency

comparator’s function is to adjust the voltage presented to

the VCO until the feedback signal’s frequency (and phase)

match that of the reference signal. When this “phase-locked”

condition exists, the RF VCO’s frequency will be N times that

of the comparison frequency, where N is the divider ratio.

1.1 OSCILLATOR

The reference oscillator frequency for the PLL is provided by

an external reference TCXO through the OSC

IN pin. OSCIN

block can operate to 40 MHz. The inputs have a V

CC/2 input

threshold and can be driven from an external CMOS or TTL

logic gate.

1.2 REFERENCE DIVIDER (R COUNTER)

The R Counter is clocked through the oscillator block. The

maximum input frequency is 40 MHz and the maximum

output frequency is 10 MHz. The R Counter is a 10-bit

CMOS binary counter with a divide range from 2 to 1,023.

See programming description 2.2.1.

1.3 PROGRAMMABLE DIVIDER (N COUNTER)

The N counter is clocked by the small signal f

IN input. The

LMX2323 RF N counter is a 15-bit integer divider. The N

counter is configured as a 5-bit A Counter and a 10-bit B

Counter, offering a continuous integer divide range from 992

to 32,767. The LMX2323 is capable of operating from

100 MHz to 2.0 GHz with a 32/33 prescaler.

1.3.1 Prescaler

The RF inputs to the prescaler consist of the f

IN and fINB pins

which are the complimentary inputs of a differential pair

amplifier. The differential f

IN configuration can operate to

2 GHz. The input buffer drives the N counter’s ECL D-type

flip-flops in a dual modulus configuration. The LMX2323 has

a 32/33 prescaler ratio. The prescaler clocks the subsequent

CMOS flip-flop chain comprising the fully programmable A

and B counters.

1.4 PHASE/FREQUENCY DETECTOR

The phase/frequency detector is driven from the N and R

counter outputs. The maximum frequency at the phase de-

tector inputs is 10 MHz. The phase detector outputs control

the charge pumps. The polarity of the pump-up or pump-

down control is programmed using PD_POL, depending on

whether RF VCO characteristics are positive or negative

(see programming description 2.2.2). The phase detector

also receives a feedback signal from the charge pump, in

order to eliminate dead zone.

1.5 CHARGE PUMP

The phase detector’s current source output pumps charge

into an external loop filter, which then converts the charge

into the VCO’s control voltage. The charge pumps steer the

charge pump output, CP

o,toVP

(pump-up) or Ground

(pump-down). When locked, CP

o is primarily in a TRI-STATE

mode with small corrections. The RF charge pump output

current magnitude is set to 4.0 mA. The charge pump output

can also be used to output divider signals as detailed in

section 2.2.3.

1.6 MICROWIRE SERIAL INTERFACE

The programmable functions are accessed through the

MICROWIRE serial interface. The interface is made of three

functions: clock, data and latch enable (LE). Serial data for

the various counters is clocked in from data on the rising

edge of clock, into the 18-bit shift register. Data is entered

MSB first. The last bit decodes the internal register address.

On the rising edge of LE, data stored in the shift register is

loaded into one of the two appropriate latches (selected by

address bits). A complete programming description is in-

cluded in the following sections.

1.7 LOCK DETECT OUTPUT

A digital filtered lock detect function is included through an

internal digital filter to produce a CMOS logic output avail-

able on the LD output pin if selected. The lock detect output

is high when the error between the phase detector inputs is

less than 15 ns for five consecutive comparison cycles. The

lock detect output is low when the error between the phase

detector input is more than 30 ns for one comparison cycle.

An open drain, analog lock detect status generated from the

phase detector is also available on the LD output pin, if

selected. The analog lock detect output goes high when the

charge pump is inactive. It goes low when the charge pump

is active during a comparison cycle. When the PLL is in

power down mode, the LD output is always high.

1.8 POWER CONTROL

The PLL can be power controlled in two ways. The first

method is by setting the CE pin LOW. This asynchronously

powers down the PLL and TRI-STATEs the charge pump

output, regardless of the PWDN bit status. The second

method is by programming through MICROWIRE, while

keeping the CE HIGH. Programming the PWDN bit in the N

de-bias the f

IN input (to a high impedance state). The R

counter functionality also becomes disabled. The reference

oscillator block powers down when the power down bit is

asserted. The OSC

IN pin reverts to a high impedance state

when this condition exists. Power down forces the charge

pump and phase comparator logic to a TRI-STATE condition.

A power down counter reset function resets both N and R

counters. Upon powering up the N counter resumes count-

ing in “close” alignment with the R counter (the maximum

error is one prescaler cycle). The MICROWIRE control reg-

ister remains active and capable of loading and latching in

data during all of the power down modes.

LMX2323 Datasheet(PDF) 6 Page - National Semiconductor (TI)

LMX2323 Datasheet(HTML) 6 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

Datasheet Download

Related Electronics Part Number

Link URL