DATA SHEET • CX72302

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8

July 22, 2004 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101216G

frequency divide ratio of 2 provides a reference frequency of 8 MHz. Therefore:

Ninteger

=Fvco_aux

Fdiv_ref

=

400

8

=50

The value to be programmed in the Auxiliary Divider Register is:

Nreg =Ninteger – 32

= 50 – 32

=

Summary:

C1416

Figure 5. Integer-N Applications: Sample Calculation

Normal Register Write. A normal 16-bit serial interface write

occurs when CS is 16 clock cycles wide. The corresponding

16-bit modulation data is simultaneously presented to the Data

pin. The content of the Modulation Data Register is passed to the

modulation unit at the next falling edge of the divided main VCO

Short CS Through Data Pin (No Address Bits Required). A

shortened serial interface write occurs when CS is from 2 to 12

clock cycles wide. The corresponding modulation data (2 to 12

bits) is simultaneously presented to the Data pin. The Data pin is

the default pin used to enter modulation data directly in the

Modulation Data Register with shortened CS strobes. This method

of data entry eliminates the register address overhead on the

serial interface. All serial interface bits are re-synchronized

internally at the reference oscillator frequency. The content of the

Modulation Data Register is passed to the modulation unit at the

Short CS Through Mod_in Pin (No Address Bits Required). A

shortened serial interface write occurs when CS is from 2 to 12

clock cycles wide. The corresponding modulation data (2 to 12

bits) is simultaneously presented to the Mod_in pin. The Mod_in

pin is the alternate pin used to enter modulation data directly into

the Modulation Data Register with shortened CS strobes. This

mode is selected through the Modulation Control Register. This

method of data entry also eliminates the register address

overhead on the serial interface and allows a different device than

the one controlling the channel selection to enter the modulation

data (e.g., a microcontroller for channel selection and a digital

signal processor for modulation data).

All serial interface bits are re-synchronized internally at the

reference oscillator frequency and the content of the Modulation

Data Register is passed to the modulation unit at the next falling

Modulation data samples in the Modulation Data Register can be

from 2 to 12 bits long, and enable the user to select how many

distinct frequency steps are to be used for the desired modulation

scheme.

The user can also control the frequency deviation through the

modulation data magnitude offset in the Modulation Control

Register. This allows shifting of the modulation data to

NOTE: The programmable range of –0.5 to +0.5 of the main

modulator can be exceeded up to the condition where

the sum of the dividend and the modulation data conform

to:

5625

.

0

)

dividend

N

(

5625

.

0

mod

+

≤

+

≤

−

When the sum of the dividend and modulation data lie outside this

For a more detailed description of direct digital modulation

functionality, refer to the Skyworks Application Note, Direct Digital

Modulation Using the CX72300, CX72301, and CX72302 Dual

Synthesizers/PLLs (document number 101349).

Register Descriptions

This section describes the CX72302 registers. All register writes

are programmed address first, followed directly with data. MSBs

are entered first. On power-up, all registers are reset to 0x000

except registers at address 0x0 and 0x3, which are set to 0x006.

Table 1 provides a description for each of the CX72302 device

registers. For more information on register loading, refer to the

Synthesizer Register Programming section in this document.