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74LVC3GU04 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74LVC3GU04
Description  TRIPLE INVERTER
Download  16 Pages
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74LVC3GU04 Datasheet(HTML) 2 Page - NXP Semiconductors

 
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9397 750 14546
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 01 February 2005
2 of 16
Philips Semiconductors
74LVC3GU04
Triple inverter
3.
Quick reference data
[1]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(C
L × VCC
2
× f
o) = sum of outputs.
[2]
The condition is VI = GND to VCC.
4.
Ordering information
5.
Marking
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tPHL, tPLH propagation delay
inputs nA to outputs nY
CL = 30 pF; RL =1kΩ;
VCC = 1.8 V
-
2.3
-
ns
CL = 30 pF; RL = 500 Ω;
VCC = 2.5 V
-
1.8
-
ns
CL = 50 pF; RL = 500 Ω;
VCC = 2.7 V
-
2.6
-
ns
CL = 50 pF; RL = 500 Ω;
VCC = 3.3 V
-
2.3
-
ns
CL = 50 pF; RL = 500 Ω;
VCC = 5.0 V
-
1.7
-
ns
CI
input capacitance
-
5
-
pF
CPD
power dissipation
capacitance per gate
VCC = 3.3 V
[1] [2] -7
-
pF
Table 2:
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC3GU04DP
−40 °C to +125 °C
TSSOP8
plastic thin shrink small outline package; 8 leads; body
width 3 mm; lead length 0.5 mm
SOT505-2
74LVC3GU04DC
−40 °C to +125 °C
VSSOP8
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74LVC3GU04GT
−40 °C to +125 °C
XSON8
plastic extremely thin small outline package; no leads;
8 terminals; body 1
× 1.95 × 0.5 mm
SOT833-1
Table 3:
Marking codes
Type number
Marking code
74LVC3GU04DP
VU04
74LVC3GU04DC
VU4
74LVC3GU04GT
VU4


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