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WM8950 Datasheet(PDF) 33 Page - Wolfson Microelectronics plc |
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WM8950 Datasheet(HTML) 33 Page - Wolfson Microelectronics plc |
33 / 52 page Preliminary Technical Data WM8950 w PTD Rev 2.1 June 2005 33 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 MS 0 Sets the chip to be master over FRAME and BCLK 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8950 (MASTER) 4:2 BCLKDIV 000 Configures the BCLK and FRAME output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved 7:5 MCLKDIV 010 Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 R6 Clock generation control 8 CLKSEL 1 Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output Table 25 Clock Control COMPANDING The WM8950 supports A-law and µ-law companding. Companding can be enabled on the ADC audio interface by writing the appropriate value to the ADC_COMP register bit. |
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