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WM8950 Datasheet(PDF) 9 Page - Wolfson Microelectronics plc |
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WM8950 Datasheet(HTML) 9 Page - Wolfson Microelectronics plc |
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9 / 52 page  Preliminary Technical Data WM8950 w PTD Rev 2.1 June 2005 9 Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25 oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information FRAME propagation delay from BCLK falling edge tDL 10 ns ADCDAT propagation delay from BCLK falling edge tDDA 10 ns AUDIO INTERFACE TIMING – SLAVE MODE Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25 oC, Slave Mode, fs=48kHz, MCLK= 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns FRAME set-up time to BCLK rising edge tLRSU 10 ns FRAME hold time from BCLK rising edge tLRH 10 ns Note: BCLK period should always be greater than or equal to MCLK period. |
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