SPICE Device Model Si4532ADY

Vishay Siliconix

This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate

data sheet of the same number for guaranteed specification limits.

Document Number: 70551

www.vishay.com

16-May-04

1

N- and P-Channel 30-V (D-S) MOSFET

CHARACTERISTICS

• N- and P-Channel Vertical DMOS

• Macro Model (Subcircuit Model)

• Level 3 MOS

• Apply for both Linear and Switching Application

• Accurate over the −55 to 125°C Temperature Range

• Model the Gate Charge, Transient, and Diode Reverse Recovery

Characteristics

DESCRIPTION

The

attached

spice

model

describes

the

typical

electrical

characteristics of the n- and p-channel vertical DMOS.

The

subcircuit

model

is

extracted

and

optimized

over

the

−55 to 125°C temperature ranges under the pulsed 0 to 10V gate

drive. The saturated output impedance is best fit at the gate bias

near the threshold voltage.

A novel gate-to-drain feedback capacitance network is used to model

the gate charge characteristics while avoiding convergence difficulties

to provide a best fit to the measured electrical data and are not

intended as an exact physical interpretation of the device.

SUBCIRCUIT MODEL SCHEMATIC