This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under

any patent accompany the sale of the product.

Rev. 1.0 Dec 16, 2004

1/10

Features

PEEL™ 18CV8Z-25

CMOS Programmable Electrically Erasable Logic Device

Ultra Low Power Operation

- Vcc = 5 Volts ±10%

- Icc = 10 µA (typical) at standby

- Icc = 2 mA (typical) at 1 MHz

CMOS Electrically Erasable Technology

- Superior factory testing

Application Versatility

Architectural Flexibility

General Description

The PEEL™18CV8Z is a Programmable Electrically Erasable

Logic (PEEL™) SPLD (Simple Programmable Logic Device)

that features ultra-low, automatic “zero” power-down operation.

The “zero power” (100 µA max. Icc) power-down mode makes the

PEEL™18CV8Z ideal for a broad range of battery-powered

portable equipment applications, from hand-held meters to PCM-

CIA modems. EE-reprogrammability provides both the conve-

nience of fast reprogramming for product development and quick

product personalization in manufacturing, including Engineering

Change Orders.

Figure 7 Pin Configuration

The PEEL™18CV8Z is logically and functionally similar to

Anachip’s 5 Volt PEEL™18CV8 and 3 Volt PEEL™18LV8Z.

The

differences

between

the

PEEL™18CV8Z

and

PEEL™18CV8 include the addition of programmable clock

polarity, a product term clock, and variable width product terms in

the AND/OR Logic Array.

Like the PEEL™18CV8, the PEEL™18CV8Z is logical superset

of the industry standard PAL16V8 SPLD. The PEEL™18CV8Z

provides additional architectural features that allow more logic to

be incorporated into the design. Anachip’s JEDEC file translator

allows easy conversion of existing 20 pin PLD designs to the

PEEL™18CV8Z architecture without the need for redesign. The

PEEL™18CV8Z architecture allows it to replace over twenty

standard 20-pin DIP, SOIC, TSSOP and PLCC packages.

I/CLK

1

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

GND

10

20

VCC

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

I/O

12

I/O

11

I

Figure 8 Block Diagram

CLK MUX (Optional)

DIP

™

TSSOP

PLCC

SOIC