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PEEL18CV8Z Datasheet(PDF) 3 Page - Anachip Corp

Part No. PEEL18CV8Z
Description  CMOS Programmable Electrically Erasable Logic Device
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Maker  ANACHIP [Anachip Corp]
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PEEL18CV8Z Datasheet(HTML) 3 Page - Anachip Corp

 
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Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Dec 16, 2004
3/10
Function Description
The PEEL™18CV8Z implements logic functions as sum-of-
products expressions in a programmable-AND/fixed-OR logic
array. User-defined functions are created by programming the
connections of input signals into the array. User-configurable
output structures in the form of I/O macrocells further increase
logic flexibility.
Architecture Overview
The PEEL™18CV8Z architecture is illustrated in the block dia-
gram of Figure 8. Ten dedicated inputs and 8 I/Os provide up to
18 inputs and 8 outputs for creation of logic functions. At the core
of the device is a programmable electrically-erasable AND array
that drives a fixed OR array. With this structure, the
PEEL™18CV8Z can implement up to eight sum-of-products
logic expressions.
Associated with each of the eight OR functions is an I/O macro-
cell that can be independently programmed to one of 12 different
configurations. The programmable macrocells allow each I/O to be
used to create sequential or combinatorial logic functions of
active-high or active-low polarity, while providing three different
feedback paths into the AND array.
AND/OR Logic Array
The programmable AND array of the PEEL™18CV8Z (shown in
Figure 9) is formed by input lines intersecting product terms. The
input lines and product terms are used as follows:
36 Input Lines:
– 20 input lines carry the true and complement of the signals
applied to the 10 input pins
– 16 additional lines carry the true and complement values of
feedback or input signals from the 8 I/Os
113 product terms:
– 102 product terms are used to form sum of product functions
– 8 output enable terms (one for each I/O)
– 1 global synchronous preset term
– 1 global asynchronous clear term
– 1 programmable clock term
At each input-line/product-term intersection, there is an
EEPROM memory cell that determines whether or not there is a
logical connection at that intersection. Each product term is
essentially a 36-input AND gate. A product term that is con-
nected to both the true and complement of an input signal will
always be FALSE and thus will not affect the OR function that it
drives. When all the connections on a product term are opened, a
“don’t care” state exists and that term will always be TRUE. When
programming the PEEL™18CV8Z, the device program- mer first
performs a bulk erase to remove the previous pattern. The erase
cycle opens every logical connection in the array. The device is
configured to perform the user-defined function by pro- gramming
selected connections in the AND array. (Note that PEEL™
device programmers automatically program all of the connections
on unused product terms so that they will have no
effect on the output function).
Variable Product Term Distribution
The PEEL™18CV8Z provides 113 product terms to drive the
eight OR functions. These product terms are distributed among the
outputs in groups of 8, 10, 12, 14, and 16 to form logical sums
(see Figure 9). This distribution allows optimum use of the
device resources.
Programmable I/O Macrocell
The unique twelve-configuration output macrocell provides com-
plete control over the architecture of each output. The ability to
configure each output independently lets you to tailor the config-
uration of the PEEL™18CV8Z to the precise requirements of
your design.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 9, consists of a D-type
flip-flop and two signal-select multiplexers. The configuration of
each macrocell is determined by the four EEPROM bits control-
ling these multiplexers. These bits determine output polarity, out-
put type (registered or non-registered) and input-feedback path
(bidirectional I/O, combinatorial feedback). Refer to Table 1 for
details.
Equivalent circuits for the twelve macrocell configurations are
illustrated in Figure 11. In addition to emulating the four PAL-
type output structures (configurations 3, 4, 9, and 10), the macro-
cell provides eight additional configurations. When creating a
PEEL™ device design, the desired macrocell configuration is
generally specified explicitly in the design file. When the design is
assembled or compiled, the macrocell configuration bits are
defined in the last lines of the JEDEC programming file.
Output Type
The signal from the OR array can be fed directly to the output pin
(combinatorial function) or latched in the D-type flip-flop (regis-
tered function). The D-type flip-flop latches data on the rising
edge of the clock and is controlled by the global preset and clear
terms. When the synchronous preset term is satisfied, the Q out-
put of the register is set HIGH at the next rising edge of the clock
input. Satisfying the asynchronous clear sets Q LOW, regardless of
the clock state. If both terms are satisfied simultaneously, the clear
will override the preset.
Output Polarity
Each macrocell can be configured to implement active-high or
active-low logic. Programmable polarity eliminates the need for
external inverters.
Output Enable
The output of each I/O macrocell can be enabled or disabled
under the control of its associated programmable output enable
product term. When the logical conditions programmed on the
output enable term are satisfied, the output signal is propagated to


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