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NTE7134 Datasheet(PDF) 4 Page - NTE Electronics

Part No. NTE7134
Description  Integrated Circuit Horizontal and Vertical Deflection Controller for Monitors
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Maker  NTE [NTE Electronics]
Homepage  http://www.nteinc.com
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NTE7134 Datasheet(HTML) 4 Page - NTE Electronics

 
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Electrical Characteristics (Cont’d): (VP = 12V, TA = +25°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Video Clamping/Vertical Blanking Output (Cont’d) [CLCB (Pin16)]
Temperature Coefficient of Vblank(CLBL)
TCblank
+2
mV/K
Output Voltage During Vertical Scan
Vscan(CLBL)
ICLBL = 0
0.59
0.63
0.67
V
Temperature Coefficient of Vscan(CLBL)
TCscan
–2
mV/K
Internal Sink Current
Isink(CLBL)
2.4
mA
External Load Current
Iload(CLBL)
–3.0
mA
Selection of Leading/Trailing Edge for Video Clamping Pulse
Voltage at CLSEL (Pin10) for Trigger with
Leading Edge of Horizontal Sync
VCLSEL
7
VCC
V
Voltage at CLSEL (Pin10) for Trigger with
Trailing Edge of Horizontal Sync
0
5
V
Delay Between Leading Edge of
Horizontal Sync and Start of
Horizontal Clamping Pulse
td(clamp)
VCLSEL > 7V
300
ns
Delay Between Leading Trailing of
Horizontal Sync and Start of
Horizontal Clamping Pulse
VCLSEL < 5V
130
ns
Maximum Duration of Video Clamping
tclamp(max)
VCLBL = 3V, VCLSEL > 7V
0.15
µs
Pulse After End of Horizontal Sync
VCLBL = 3V, VCLSEL > 5V
1.0
µs
Input Resistance at CLSEL (Pin10)
RCLSEL
VCLSEL ≤ VCC
80
k
PLL1 Phase Comparator and Frequency–Locked Loop [HPLL1 (Pin26) and HBUF (Pin27)]
Maximum Width of Horizontal Sync Pulse
tHSYNC(max)
fH < 45kHz, Note 2
20
&
(Referenced to Line Period)
fH > 45kHz, Note 3
25
%
Total Lock–In Time of PLL1
tlock(HPLL1)
40
80
ms
Control Voltage
VHPLL1
Note 4, Note 5
Buffered f/v Voltage at HBUF (Pin27)
VHBUF
fH(min), Note 6
5.6
V
fH(max), Note 6
2.5
V
Maximum Load Current
Iload(HBUF)
–4.0
mA
Adjustment of Horizontal Picture Position
Horizontal Shift Adjustment Range
∆HPOS
IHSHIFT = 0
–10.5
%
(Referenced to Horizontal Period)
IHSHIFT = –135µA
+10.5
%
Input Current
IHPOS
∆HPOS = +10.5%
–110
–120
–135
µA
∆HPOS = –10.5%
0
µA
Note 3. To ensure safe locking of the horizontal oscillator, one of the following procedures is required:
a) Search mode starts always from fmin. Then the PLL1 filter components are a 3.3nF
capacitor from Pin26 to GND in parallel with an 8.2k
Ω resistor in series with a 47nF
capacitor.
b) Search mode starts either from fmin or fmax with HPOS in middle position (IHPOS = 60µA).
Then the PLL1 filter components are a 1.5nF capacitor from Pin26 to GND in parallel
with a 27k
Ω resistor in series with a 47nF capacitor.
c) After locking is achieved, HPOS can be operated in the normal way
Note 4. Loading of HPLL1 (Pin26) is not allowed.
Note 5. Oscillator frequency is fmin when no sync signal is present (no continuous blanking at Pin16).
Note 6. Voltage at HPPL1 (Pin26) is fed to HBUF (Pin27) via a buffer. Disturbances caused by hori-
zontal sync are removed by an internal sample–and–hold circuit.


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