Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

NTE7133 Datasheet(PDF) 5 Page - NTE Electronics

Part No. NTE7133
Description  Integrated Circuit Horizontal and Vertical Deflection Controller for VGA/XGA and Autosync Monitors
Download  7 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  NTE [NTE Electronics]
Homepage  http://www.nteinc.com
Logo 

NTE7133 Datasheet(HTML) 5 Page - NTE Electronics

   
Zoom Inzoom in Zoom Outzoom out
 5 / 7 page
background image
Functional Description:
Horizontal Sync Separator and Polarity Correction
An AC–coupled video signal or a DC–coupled TTL sync signal (H only or composite sync) is input
on Pin9. Video signals are clamped with top sync on 12.8V, and are sliced at 1.4V. This results in a
fixed absolute slicing level of 120mV relative to top sync.
DC–coupled TTL sync signals are also sliced at 1.4V, however with the clamping circuit in current limi-
tation. The polarity of the separated sync is detected by internal integration of the signal, then the po-
larity is corrected.
The polarity information is fed to the VGA mode detector. The corrected sync is the input signal for
the vertical sync integrator and the PLL1 stage.
Vertical Sync Separaztor, Polarity Correction and Vertical Sync Integrator
DC–coupled vertical TTL sync signals may be applied to Pin10. They are sliced at 1.4V. The polarity
of the separated sync is detected by internal integration, then polarity is corrected. The polarity infor-
mation is fed to the VGA mode detector. If Pin10 is not used, it must be connected to GND.
The separated Vi sync signal from Pin10, or the integrated composite sync signal from Pin9 (TTL or
video) directly triggers the vertical oscillator.
VGA Mode Detector and Mode Output
The three standard VGA modes and a 4th not fixed mode are decoded by the polarities of the horizon-
tal and the vertical sync input signals. An external resistor (from VP to Pin7) is necessary to match
this function. In all three VGA modes the correxct amplitudes are activated. The presence of the 4th
mode is indicated by HIGH on Pin7. This signal can be used externally to switch any horizontal or
vertical parameters.
VGA Mode Detector Input
For autosync operation the voltage on Pin7 must be externally forced to a level of < 50mV. Vertical
amplitude pre–settings for VGA are then inhibited. The delay time between vertical trigger pulse and
the start of vertical deflection changes from 575 to 300
µs (575µs is needed for VGA). The vertical
amplitude then remains constant in a frequency range from 50 to 110Hz.
Clamping and V–Blanking Generator
A combined clamping and V–blanking pulse is available on Pin8. The lower level of 1.9V is the blank-
ing signal derived from the vertical blanking pulse from the internal vertical oscillator.
Vertical blanking equals the delay between vertical sync and the start of vertical scan. By this, an opti-
mum blanking is acheived for VGA/XGA as well as for multi–frequency operation (selectable via
Pin7).
The upper level of 5.4V is the horizontal clamping pulse with internally fixed pulse width of 0.8
µs. A
mono flop, which is triggered by the trailing edge of the horizontal sync pulse, generates this pulse.
If composite sync is applied one clamping pulse per H–period is generated during V–sync. The pahse
of the clamping pulse may change during V–sync.
PLL1 Phase Detector
The phase detector is a standard one using switched current sources. The middle of the sync is
compared with a fixed point of the oscillator sawtooth voltage. The PLL filter is connected to Pin17.
If composite sync is applied, the distributed control voltage is corrected during V–sync.
Horizontal Oscillator
This oscillator is a relaxation type and requires a fixed capacitor of 10nF at Pin19. By changing the
current into Pin18 the whole frequency range from 13 to 100kHz can be covered.
The current can be generated either by a frequency to voltage converter or by a resistor. A frequency
adjustment may also be added if necessary.
The PLL1 control voltage at Pin17 moduloates via a buffer stage the oscillator thresholds. A high DC–
loop gaqin ensures a stable phase relationship between horizontal sunc and line flyback pulses.


Html Pages

1  2  3  4  5  6  7 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn