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MAX1471 Datasheet(PDF) 4 Page - Maxim Integrated Products

Part # MAX1471
Description  315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX1471 Datasheet(HTML) 4 Page - Maxim Integrated Products

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315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
4
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, AVDD = DVDD = HVIN = +2.4V to +3.6V, fRF = 300MHz to 450MHz, TA = -40°C to +125°C, unless otherwise
noted. Typical values are at AVDD = DVDD = HVIN = +3.0V, fRF = 434 MHz, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG BASEBAND
Maximum Data Filter Bandwidth
BWDF
50
kHz
Maximum Data Slicer Bandwidth
BWDS
100
kHz
Maximum Peak Detector
Bandwidth
BWPD
50
kHz
Manchester coded
33
Maximum Data Rate
Nonreturn to zero (NRZ)
66
kbps
CRYSTAL OSCILLATOR
Crystal Frequency
fXTAL
9.04
13.728
MHz
Frequency Pulling by VDD
3
ppm/V
Maximum Crystal Inductance
50
µH
Crystal Load Capacitance
3pF
DIGITAL INTERFACE TIMING (see Figure 8)
Minimum SCLK Setup to Falling
Edge of CS
tSC
30
ns
Minimum CS Falling Edge to
SCLK Rising-Edge Setup Time
tCSS
30
ns
Minimum CS Idle Time
tCSI
125
ns
Minimum CS Period
tCS
2.125
µs
Maximum SCLK Falling Edge to
Data Valid Delay
tDO
80
ns
Minimum Data Valid to SCLK
Rising-Edge Setup Time
tDS
30
ns
Minimum Data Valid to SCLK
Rising-Edge Hold Time
tDH
30
ns
Minimum SCLK High Pulse Width
tCH
100
ns
Minimum SCLK Low Pulse Width
tCL
100
ns
Minimum CS Rising Edge to
SCLK Rising-Edge Hold Time
tCSH
30
ns
Maximum CS Falling Edge to
Output Enable Time
tDV
25
ns
Maximum CS Rising Edge to
Output Disable Time
tTR
25
ns
Note 1: Production tested at TA = +85°C. Guaranteed by design and characterization over entire temperature range.
Note 2: Guaranteed by design and characterization. Not production tested.
Note 3: The oscillator register (0x3) is set to the nearest integer result of fXTAL / 100kHz (see the Oscillator Frequency Register section).
Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 15nH inductive degeneration
from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from the LNA
source to ground. The equivalent input circuit is 50
Ω in series with 2.2pF. The voltage conversion gain is measured with the
LNA input matching inductor, the degeneration inductor, and the LNA/mixer resonator in place, and does not include the IF fil-
ter insertion loss.


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