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LTC4221 Datasheet(PDF) 21 Page - Linear Technology |
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LTC4221 Datasheet(HTML) 21 Page - Linear Technology |
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21 / 28 page  21 LTC4221 4221f 0.4V VTH 1.234V 1.9µA 20µA <9.5µA 9.5µA 9.5µA DISCHARGE BY LOAD 4221 F14 0.851V 0.4V 1.234V 12 VCCn VONn VTIMER VGATE2 VOUT2 IRSENSE2 34 5 6 7 8 9 A REGULATED AT 25mV/RSENSE REGULATED AT VSENSE(ACL)(t)/RSENSE RESET STATE INITIAL TIMING CHANNEL 2 START-UP NORMAL CYCLE Start-Up Cycle With Current Limit During a channel start-up cycle, if the inrush current as according to Equation (12) is large enough to cause a voltage drop greater than the active current limit threshold (VSENSE(ACL)) across the sense resistor, an internal servo loop controls the operation of the 9.5µA current source at the GATE pin to regulate the load current to: I V R INRUSH SENSE ACL SENSE = () (13) The active current limit threshold for channel n has a component controlled by the voltage at the FB n pin. When FB n = 0V, VSENSE(ACL) = 9mV. As VOUTn and FBn ramp up, VSENSE(ACL) increases linearly until FBn reaches 0.5V, where VSENSE(ACL) saturates at 25mV. In this fashion, the inrush current is controlled by this “foldback” limiting that tends to keep the power dissipation in the external MOSFET constant during the start-up cycle. The timing diagram in Figure 14 illustrates the operation of the LTC4221 in a channel start-up cycle with limited inrush current as described by Equation 13. Between time points 5 and 6, the GATE2 pin ramps up with IGATE = 9.5µA. At time point 6, the inrush current increases enough to trip VSENSE(ACL)(t) and an internal servo loop engages, limiting the inrush current to the level as in Equation 13 by decreasing IGATE (<9.5µA). As a result, the ramp rate of both VGATE2 and VOUT2 decreases and VSENSE2 increases linearly until it saturates at 25mV at time point 7. At time point 8, the external MOSFET enters triode operation. IINRUSH drops as the ramp rate of VOUT2 falls below that of VGATE2 so IGATE reverts back to 9.5µA. At time point 9, the internal servo loop to control IINRUSH is disengaged and channel 2 slow comparator is armed, ending the channel 2 start-up cycle. So if CLOAD2 is not fully charged up at this point, IINRUSH will be subject to the slow comparator threshold and actions as outlined in the Electronic Circuit Breaker section. For a successful channel start-up, the current limited part of the VOUT ramp-up (time points 6 and 8 of Figure 14) must not exceed the sum of start-up cycle delay as given by Equation 10 and the slow comparator response time as given by Equation 1. An example of an unsuccessful start-up is Figure 11 which shows a channel powering up into an overcurrrent at the load. The fast comparators of both channels are armed at the end of the initial timing cycle at time point 4 of Figure 14. If a short circuit during the start-up cycle overrides the servo loop and causes VRSENSE of either channel to exceed 100mV for more than 1µs, the electronic circuit breaker trips and the LTC4221 enters the fault state. Frequency Compensation at Start-Up Cycle If a channel’s external gate input capacitance (CISS) is greater than 600pF, no external gate capacitor is required at GATE to stabilize the internal current-limiting loop dur- ing start-up with current limit. The servo loop that controls the external MOSFET during current limiting has a unity- gain frequency of about 105kHz and phase margin of 80° for external MOSFET gate input capacitances to 2.5nF. Power MOSFET Power MOSFETs can be classified by RDS(ON) at VGS gate drive ratings of 10V, 4.5V, 2.5V and 1.8V. Those rated for RDS(ON) at 10V VGS usually have a higher VGS absolute maximum rating than those at 4.5V and 2.5V. At low APPLICATIO S I FOR ATIO Figure 14. Channel 2 Start-Up with Current Limit |
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Similar Description - LTC4221 |
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