Signal Trace

Uninterrupted Ground Plane

Signal Trace

Uninterrupted Ground Plane

Signal Via

Ground Via

Layer 6

Layer 1

0402

0402

IN±

IN+

(a)

(b)

18

DSLVDS1002

SNLS619 – JULY 2018

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Copyright © 2018, Texas Instruments Incorporated

Layout Guidelines (continued)

important for heat dissipation makes the optimal decoupling layout impossible to achieve due to insufficient pad-

to-dap spacing as shown in Figure 13(b). When this occurs, placing the decoupling capacitor on the backside of

as possible while still allowing for sufficient solder mask coverage. If the via is left open, solder may flow from the

pad and into the via barrel. This will result in a poor solder connection.

Figure 13. Typical Decoupling Capacitor Layouts

12.2 Layout Example

At least two or three times the width of an individual trace should separate single-ended traces and differential

pairs to minimize the potential for crosstalk. Single-ended traces that run in parallel for less than the wavelength

of the rise or fall times usually have negligible crosstalk. Increase the spacing between signal paths for long

parallel runs to reduce crosstalk. Boards with limited real estate can benefit from the staggered trace layout, as

shown in Figure 14.

Figure 14. Staggered Trace Layout

This configuration lays out alternating signal traces on different layers; thus, the horizontal separation between

traces can be less than 2 or 3 times the width of individual traces. To ensure continuity in the ground signal path,

TI recommends having an adjacent ground via for every signal via, as shown in Figure 15. Note that vias create

additional capacitance. For example, a typical via has a lumped capacitance effect of 1/2 pF to 1 pF in FR4.

Figure 15. Ground Via Location (Side View)

Short and low-impedance connection of the device ground pins to the PCB ground plane reduces ground

bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create

discontinuities that increase returning current loop areas.

To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and

so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the

same area, as opposed to mixing them together, helps reduce susceptibility issues.