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SLRC610 Datasheet(PDF) 9 Page - NXP Semiconductors |
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SLRC610 Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 145 page  NXP Semiconductors SLRC610 High-performance ICODE frontend SLRC610 and SLRC610 plus SLRC610 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved. Product data sheet Rev. 4.5 — 27 June 2018 COMPANY PUBLIC 227645 9 / 145 The TxIRQ bit in register IRQ0 indicates that the transmission is finished. If the state changes from sending data to transmitting the end of the frame pattern, the transmitter unit sets the interrupt bit automatically. The bit RxIRQ in register IRQ0 indicates an interrupt when the end of the received data is detected. The bit IdleIRQ in register IRQ0 is set if a command finishes and the content of the command register changes to idle. The register WaterLevel defines both - minimum and maximum warning levels - counting from top and from bottom of the FIFO by a single value. The bit HiAlertIRQ in register IRQ0 is set to logic 1 if the HiAlert bit is set to logic 1, that means the FIFO data number has reached the top level as configured by the register WaterLevel and bit WaterLevelExtBit. The bit LoAlertIRQ in register IRQ0 is set to logic 1 if the LoAlert bit is set to logic 1, that means the FIFO data number has reached the bottom level as configured by the register WaterLevel. The bit ErrIRQ in register IRQ0 indicates an error detected by the contactless UART during receive. This is indicated by any bit set to logic 1 in register Error. The bit LPCDIRQ in register IRQ0 indicates a card detected. The bit RxSOFIRQ in register IRQ0 indicates a detection of a SOF or a subcarrier by the contactless UART during receiving. The bit GlobalIRQ in register IRQ1 indicates an interrupt occurring at any other interrupt source when enabled. Table 5. Interrupt sources Interrupt bit Interrupt source Is set automatically, when Timer0IRQ Timer Unit the timer register T0 CounterVal underflows Timer1IRQ Timer Unit the timer register T1 CounterVal underflows Timer2IRQ Timer Unit the timer register T2 CounterVal underflows Timer3IRQ Timer Unit the timer register T3 CounterVal underflows TxIRQ Transmitter a transmitted data stream ends RxIRQ Receiver a received data stream ends IdleIRQ Command Register a command execution finishes HiAlertIRQ FIFO-buffer pointer the FIFO data number has reached the top level as configured by the register WaterLevel LoAlertIRQ FIFO-buffer pointer the FIFO data number has reached the bottom level as configured by the register WaterLevel ErrIRQ contactless UART a communication error had been detected LPCDIRQ LPCD a card was detected when in low-power card detection mode RxSOFIRQ Receiver detection of a SOF or a subcarrier GlobalIRQ all interrupt sources will be set if another interrupt request source is set |
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