HY62U8400ALLT2-I datasheet(2/11 Pages) HYNIX

Part #	HY62U8400ALLT2-I

Description	512Kx8bit CMOS SRAM

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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HY62U8400A Series

Rev 07 / Apr. 2001

2

DESCRIPTION

The HY62U8400A is a high-speed, low power and

4M bits CMOS SRAM organized as 512K words

by 8 bits. The HY62U8400A uses Hynix's high

performance twin tub CMOS process technology

and was designed for high-speed and low power

circuit technology. It is particularly well suited for

use in high-density and low power system

applications. This device has a data retention

mode that guarantees data to remain valid at the

minimum power supply voltage of 2.0V.

FEATURES

• Fully static operation and Tri-state outputs

• TTL compatible inputs and outputs

• Low power consumption

• Battery backup(LL-part)

-. 2.0V(min) data retention

• Standard pin configuration

-. 32pin 525mil SOP

-. 32pin 400mil TSOP-II

(Standard and Reversed)

Product

Voltage

Speed

Operation

Standby Current(uA)

Temperature

No.

(V)

(ns)

Current/Icc(mA)

LL

(

°C)

HY62U8400A

2.7~3.3

70*/85/100

5

20

0~70

HY62U8400A-E

2.7~3.3

70*/85/100

5

30

-25~85

HY62U8400A-I

2.7~3.3

70*/85/100

5

30

-40~85

Note 1. Current value is max.

* 70ns is available with 30pF test load

PIN CONNECTION

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Vcc

A15

/WE

A13

A8

A9

A11

/OE

A10

/CS

I/O8

I/O7

I/O6

I/O5

I/O4

A18

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

I/O3

Vss

A17

A18

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

I/O3

Vss

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Vcc

A15

/WE

A13

A8

A9

A11

/OE

A10

/CS

I/O8

I/O7

I/O6

I/O5

I/O4

A17

Vcc

A15

/WE

A13

A8

A9

A11

/OE

A10

/CS

I/O8

I/O7

I/O6

I/O5

I/O4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

A18

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

I/O3

Vss

SOP

TSOP-II (Standard)

TSOP-II (Reversed)

PIN DESCRIPTION

BLOCK DIAGRAM

Pin Name

Pin Function

/CS

Chip Select

/WE

Write Enable

/OE

Output Enable

A0 ~ A18

Address Input

I/O1 ~ I/O8

Data Input/Output

Vcc

Power(2.7~3.3V)

Vss

Ground

MEMORY ARRAY

512Kx 8

ROW DECODER

I/O1

I/O8

A0

A18

/CS

/OE

/WE

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