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GC1115 Datasheet(PDF) 54 Page - Texas Instruments |
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GC1115 Datasheet(HTML) 54 Page - Texas Instruments |
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54 / 80 page  www.ti.com Snapshot RAM Registers (Addresses 96 – 119) GC1115 SLWS144 – FEBRUARY 2005 SNAP_A_CONTROL 0x60 (96) Type: Read/Write Value at RESET: 0x0000 The SNAP_A_CONTROL register controls the operation of Snapshot RAM A, including the selection of its data source and the type of data being captured. When using Snapshot RAM A in histogram mode, the RAM must first be cleared by writing a 0x0002 to SNAP_A_CONTROL. If the GC1115 is operating in two-channel mode, Snapshot RAM A can monitor the samples of either Channel 0 or Channel 1. Snapshot RAM A will not begin a capture or histogram until the SNAP_A_SYNC event occurs. SNAP_A_SYNC cannot be triggered by a periodic TIMER event. BITS DESCRIPTION [1:0] Snapshot RAM A command: 00 – DISABLE (ignore all other bits in word) 01 – ENABLE (observe all other bits) 1x – CLEAR_RAM (ignore all other bits) 2 Two-channel data source: 0 = Channel 0 1 = Channel 1 [5:3] Snapshot RAM A data source: 001: input 010: after Stage 1 011: after Stage 2 100: after Stage 3 101: after Stage 4 [7:6] Snapshot RAM A operating mode: 00 = capture 1k samples 01 = histogram I samples 10 = histogram Q samples 11 = histo. mag2(I + jQ) [15:8 Reserved ] SNAP_A_STATUS 0x61 (97) Type: Read only Value at RESET: 0x0000 The SNAP_A_STATUS register can be read to determine the current status (state) of Snapshot RAM A. After sending a 0x2 command (clear RAM) to SNAP_A_CONTROL, SNAP_A_STATUS can be polled to determine when the RAM has been cleared. After a Snapshot RAM A capture completes, the microprocessor or DSP can receive an interrupt by enabling bit 0 of INT_MASK. During histogram operation, if one or more Snapshot RAM A histogram bins overflows its 32-bit count, bit 2 of INT_MAP will be set. If bit 2 of INT_MASK is set, a Snapshot RAM A bin overflow will also generate an interrupt. Snapshot RAM A will not begin a capture or histogram until the SNAP_A_SYNC event occurs. SNAP_A_SYNC cannot be triggered by a periodic TIMER event. BITS DESCRIPTION [2:0] Snapshot RAM A 000 – OFF 001 – enabled (waiting) status: 010 – active (capturing) 011 – capture complete 100 – resetting (clearing all snapshot RAM bins) [15:3] Reserved 54 |
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