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PS8466

05/03/00

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PI6C185-01B

Precision 1-5 Clock Buffer

1.5V

1.5V

1.5V

1.5V

Input

Waveform

Output

Waveform

Output

Buffer

Test

Point

2.4

1.5

0.4

tSDKH

tSDKP

3.3V

Clocking

Interface

(TTL)

tSDKL

Test Load

Figure 1. Clock Waveforms

Notes:

1. Maximum rise/fall times are guaranteed at maximum specified load.

2. Minimum rise/fall times are guaranteed at minimum specified load.

3. Rise/fall times are specified with pure capacitive load as shown.

Testing is done with an additional 500

Ω resistor in parallel.

Minimum and Maximum Expected Capacitive Loads

Design Guidelines to Reduce EMI

1. Place R

value for CI is 10pF. R

and fall time are still within the specified values.

2. Minimize the number of “vias” of the clock traces.

3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing

clock traces from plane to plane (refer to rule #2).

4. Position clock signals away from signals that go to any cables or any external connectors.

k

c

o

l

Cd

a

o

L

n

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Md

a

o

L

x

a

Ms

ti

n

Us

e

t

o

N

M

A

R

D

S5

10

2F

pn

o

it

a

ci

fi

c

e

p

S

M

M

I

D

M

A

R

D

S