Document Number: 002-16365 Rev. *C

Page 7 of 36

CYW20737

1.7 ADC Port

The CYW20737 contains a 16-bit ADC (effective number of bits is 10).

Additionally:

The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital hardware that processes

the output of the ADC core into valid ADC output samples. Directed by the firmware, the digital hardware also controls the input

The ADC input range is selectable by firmware control:

ADC modes are defined in Table 2.

Table 2. ADC Modes

Mode

ENOB (Typical)

Maximum Sampling Rate (kHz)

a. Settling time after switching channels.

0

13

5.859

171

1

12.6

11.7

85

212

46.875

21

3

11.5

93.75

11

410

187

5